Artesyn MVME5100, Programmer'S Reference Manual, Page: 121 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
121
2.4.15.2 Reset State
After power on reset, the MPIC state is:

Current task priority for all CPUs set to 15.

All interrupt source priorities set to zero.

All interrupt source mask bits set to a one.

All interrupt source activity bits cleared.

Processor Init Register is cleared.

All counters stopped and interrupts disabled.

Controller mode set to 8259 pass-through.
2.4.16 Operation
This sections discusses the following topics:

Interprocessor Interrupts on page 121

Dynamically Changing I/O Interrupt Configuration on page 122

EOI Register on page 122

Interrupt Acknowledge Register on page 122

8259 Mode on page 122

Current Task Priority Level on page 123
2.4.16.1 Interprocessor Interrupts
Four interprocessor interrupt (IPI) channels are provided for use by all processors. During
system initialization the IPI vector/priority registers for each channel should be programmed
to set the priority and vector returned for each IPI event. During system operation a processor
may generate an IPI by writing a destination mask to one of the IPI dispatch registers. Note that
each IPI dispatch register is shared by both processors. Each IPI dispatch register has two
addresses but they are shared by both processors. That is there is a total of four IPI dispatch
registers in the MPIC.
The IPI mechanism may be used for self interrupts by programming the dispatch register with
the bit mask for the originating processor.