Artesyn MVME5100, Programmer'S Reference Manual, Page: 138 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
138
Default PPC Master ID. This bit determines which MCHK_ pin will be asserted for error
conditions in which the PPC Master ID cannot be determined or the PHB was the PPC Master.
For example, in the event of a PCI parity error for a transaction in which the PHB’s PCI Master
was not involved, the PPC Master ID cannot be determined. When DFLT is set, MCHK1_ is used.
When DFLT is clear, MCHK0_ will be used.
XBTOM
PPC Address Bus Time-out Machine Check Enable. When this bit is set, the XBTO bit in the
ESTAT register will be used to assert the MCHK output to the current address bus master. When
this bit is clear, MCHK will not be asserted.
XDPEM
PPC Data Parity Error Machine Check Enable. When this bit is set, the XDPE bit in the ESTAT
register will be used to assert the MCHK output to the current address bus master. When this
bit is clear, MCHK will not be asserted.
PPERM
PCI Parity Error Machine Check Enable. When this bit is set, the PPER bit in the ESTAT register
will be used to assert the MCHK output to bus master 0. When this bit is clear, MCHK will not be
asserted.
PSERM
PCI System Error Machine Check Enable. When this bit is set, the PSER bit in the ESTAT register
will be used to assert the MCHK output to bus master 0. When this bit is clear, MCHK will not be
asserted.
PSMAM
PCI Signalled Master Abort Machine Check Enable. When this bit is set, the PSMA bit in the
ESTAT register will be used to assert the MCHK output to the bus master which initiated the
transaction. When this bit is clear, MCHK will not be asserted.
PRTAM PCI Master Received Target Abort Machine Check Enable. When this bit is set, the PRTA
bit in the ESTAT register will be used to assert the MCHK output to the bus master which
initiated the transaction. When this bit is clear, MCHK will not be asserted.
XBTOI