Artesyn MVME5100, Programmer'S Reference Manual, Page: 90 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
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The PHB performs spread I/O addressing when the MEM bit is clear and the IOM bit is set. The
PHB takes the PPC address, applies the offset specified in the MSOFFx register, and maps the
result to PCI as shown in the following figure.
Spread I/O addressing allows each PCI device’s I/O registers to reside on a different PPC
memory page, so device drivers can be protected from each other using memory page
protection.
All I/O accesses must be performed within natural word boundaries. Any I/O access that is not
contained within a natural word boundary results in unpredictable operation. For example, an
I/O transfer of four bytes starting at address $80000010 is considered a valid transfer. An I/O
transfer of four bytes starting at address $80000011 is considered an invalid transfer since it
crosses the natural word boundary at address $80000013/$80000014.
Generating PCI Configuration Cycles
The PHB uses configuration Mechanism #1 as defined in the PCI Local Bus Specification 2.1 to
generate configuration cycles. Please refer to this specification for a complete description of
this function.
Configuration Mechanism #1 uses an address register/data register format. Performing a
configuration access is a two step process. The first step is to place the address of the
configuration cycle within the CONFIG_ADDRESS register. Note that this action does not
generate any cycles on the PCI bus.
Figure 2-7 PCI Spread I/O Address Translation