Artesyn MVME5100, Programmer'S Reference Manual, Page: 155 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
155
IO Space Enable. If set, the PHB will respond to PCI I/O accesses when appropriate. If cleared,
the PHB will not respond to PCI I/O space accesses.
MEMSP
Memory Space Enable. If set, the PHB will respond to PCI memory space accesses when
appropriate. If cleared, the PHB will not respond to PCI memory space accesses.
MSTR
Bus Master Enable. If set, the PHB may act as a master on PCI. If cleared, the PHB may not act as
a PCI Master.
PERR
Parity Error Response. If set, the PHB will check parity on all PCI transfers. If cleared, the PHB will
ignore any parity errors that it detects and continue normal operation.
SERR
System Error Enable. This bit enables the SERR_ output pin. If clear, the PHB will never drive
SERR_. If set, the PHB will drive SERR_ active when a system error is detected.
The Status Register (STATUS) is used to record information for PCI bus related events. The bits
within the STATUS register are defined as follows:
P66M
PCI66 MHz. This bit indicates the PHB is capable of supporting a 66.67 MHz PCI bus.
FAST
Fast Back-to-Back Capable. This bit indicates that the PHB is capable of accepting fast
back-to-back transactions with different targets.
DPAR
Data Parity Detected. This bit is set when the following conditions are met:

the PHB asserted PERR_ itself or observed PERR_ asserted

the PHB was the PCI Master for the transfer in which the error occurred

the PERR bit in the PCI Command Register is set