Artesyn MVME5100, Programmer'S Reference Manual, Page: 134 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
134
Park on lock. If set, the PCI Arbiter will park the bus on the master that successfully obtains a
PCI bus lock. The PCI Arbiter keeps the locking master parked and does not allow any
non-locked masters to obtain access of the PCI bus until the locking master releases the lock. If
this bit is cleared, the PCI Arbiter does not distinguish between locked and non-locked cycles.
ENA
Enable. This read only bit indicates the enabled state of the PCI Arbiter. If set, the PCI Arbiter is
enabled and is acting as the system arbiter. If cleared, the PCI Arbiter is disabled and external
logic is implementing the system arbiter. Please refer to the section titled
PHB Hardware
Configuration for more information on how this bit gets set.
2.5.1.5 Hardware Control-Status/Prescaler Adjust Register
The Hardware Control-Status Register (HCSR) provides hardware specific control and status
information for the PHB.
The bits within the HCSR are defined in the following table:
XPRx
PPC/PCI Clock Ratio. This is a read only field that is used to indicate the clock ratio that has been
established by the PHB at the release of reset.
Table 2-33 Hardware Control-Status/Prescaler Adjust Register
Address $FEFF0010
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name HCSR XPAD
XPR2 XPR1 XPR0 SP
RQ
WLR
T1
WLR
T0
RLR
T1
RLR
T0
Operation
R R R R R R R R R R R R/W R/W R/W R/W R/W
R R/W
Reset
0 0 0 0 0 X X X 0 0 0 1 0 0 0 0
$00 $9C