Artesyn MVME5100, Programmer'S Reference Manual, Page: 28 / 318

Product Data and Memory Maps
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
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The chapter discusses the following topics:

Memory Maps

System Bus

Hawk ASIC

PCI Local Bus

IPMC7xx ISA Bus Resources
1.2 Memory Maps
The following sections describe the memory maps for the MVME5100.
The section discusses the following topics:

Processor Memory Map on page 28

PCI Local Bus Memory Map on page 32

VMEbus Memory Map on page 32
1.2.1 Processor Memory Map
The processor memory map configuration is under the control of the PCI Host Bridge (PHB)
and System Memory Controller (SMC) portions of the Hawk ASIC. The Hawk adjusts system
mapping to suit a given application via programmable map decoder registers. At system
power-up or reset, a default processor memory map takes over.
Following a reset, the memory map presented to the processor is identical to the CHRP
memory map described in this document.
The MVME5100 is fully capable of supporting both the PREP and the CHRP processor memory
maps with ROM/FLASH size limited to 16MB and RAM size limited to 2GB.