Artesyn MVME5100, Programmer'S Reference Manual, Page: 77 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
77
The PPC Arbiter implements the following prioritization scheme:

HAWK (Highest Priority)

EXTL

CPUx

CPUy (Lowest Priority)
The PPC Arbiter is controlled by the XARB register within the PHB PPC60x register group.
The PPC Arbiter supports two prioritization schemes. Both schemes affect the priority of the
CPU’s with respect to each other. The CPU fixed option always places the priority of CPU0 over
CPU1. The CPU rotating option gives priority on a rotational basis between CPU0 and CPU1. In
all cases, the priority of the CPUs remains fixed with respect to the priority of HAWK and EXTL,
with HAWK always having the highest priority of all.
The PPC Arbiter supports four parking modes. Parking is implemented only on the CPUs and is
not implemented on either HAWK or EXTL. The parking options include parking on CPU0,
parking on CPU1, parking on the last CPU, or parking disabled.
There are various system level debug functions provided by the PPC Arbiter. The PPC Arbiter
has the optional ability to flatten the PPC60x bus pipeline. Flattening can be imposed uniquely
on single beat reads, single beat writes, burst reads, and burst writes. It is possible to further
qualify the ability to flatten based on whether there is a switch in masters or whether to flatten
unconditionally for each transfer type. This is a debug function only and is not intended for
normal operation.
2.3.2.6 PPC Parity
The PHB generates data parity whenever it is sourcing PPC data. This happens during PPC
Master write cycles and PPC Slave read cycles. Valid data parity is presented when DBB_ is
asserted for PPC Master write cycles. Valid data parity is presented when TA_ is asserted for PPC
Slave read cycles.
The PHB checks data parity whenever it is sinking PPC data. This happens during PPC Master
read cycles and PPC Slave write cycles. Data parity is considered valid anytime TA_ has been
asserted. If a data parity error is detected, then the PHB will latch address and attribute
information within the ESTAT, EADDR, and EATTR registers, and an interrupt or machine check
will be generated depending on the programming of the ESTAT register.