Artesyn MVME5100, Programmer'S Reference Manual, Page: 265 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
265
3.3.3.26 Address Parity Error Log Register
apelog
apelog is set when a parity error occurs on the PPC60x address bus during any PPC60x address
cycle (TS_ asserted to AACK_ asserted). It is cleared by writing a one to it or by power-up reset.
ape_tt0-4
ape_tt is the value that was on the TT0-TT4 signals when the apelog bit was set.
ape_ap0-3
APE_AP is the value that was on the AP0-AP3 signals when the apelog bit was set.
ape_me
When ape_me is set, the transition of the apelog bit from false to true causes the Hawk to pulse
its machine check interrupt request pin (MCHK0_) true. When ape_me is cleared, apelog does
not affect the MCHK0_ pin.
Table 3-46 Address Parity Error Log Register
Address $FEF800E0
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
ape
log
0 0 ape_tt0 ape_tt1 ape_tt2 ape_tt3 ape_tt4 0 0 0 0 ape_ap0 ape_ap1 ape_ap2 ape_ap3 0 0 0 0 0 0 0 ape_me
Operation
R/C R R R R R R R R R R R R R R R R R R R R R R R/W
READ ZERO
Reset
0 P X X 0 P 0 P 0 P 0 P 0 P X X X X 0 P 0 P 0 P 0 P X X X X X X X 0 PL
X