Artesyn MVME5100, Programmer'S Reference Manual, Page: 165 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
165
Bus Number. Configuration Cycles: Identifies a targeted bus number. If written with all zeros, a
Type 0 Configuration Cycle will be generated. If written with any value other than all zeros, then
a Type 1 Configuration Cycle will be generated.
Special Cycles: Identifies a targeted bus number. If written with all zeros, a Special Cycle will be
generated. If written with any value other than all zeros, then a Special Cycle translated into a
Type 1 Configuration Cycle will be generated.
EN
Enable. Configuration Cycles: Writing a one to this bit enables CONFIG_DATA to Configuration
Cycle translation. If this bit is a zero, subsequent accesses to CONFIG_DATA will be passed
though as I/O Cycles.
Special Cycles: Writing a one to this bit enablesCONFIG_DATA to Special Cycle translation. If this
bit is a zero, subsequent accesses to CONFIG_DATA will be passed though as I/O Cycles.
2.5.2.10 CONFIG_DATA Register
The description of the CONFIG_DATA register is also presented in three perspectives: from the
PCI bus, from the PPC bus in Big Endian mode, and from the PPC bus in Little Endian mode. Note
that the view from the PCI bus is purely conceptual, since there is no way to access the
CONFIG_DATA register from the PCI bus.
Table 2-67 Conceptual Perspective from the PCI bus
Offset $CFF $CFE $CFD $CFC
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CONFIG_DATA
Data ‘D’ ’ Data ‘C’ Data ‘B’ Data ‘A’
Operation R/W R/W R/W R/W
Reset n/a n/a n/a n/a
Table 2-68 Perspective from the PPC bus in Big Endian mode
Offset $CFC $CFD $CFE $CFF
Bit (DH)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name CONFIG_DATA
Data ‘A’ ’ Data ‘B’ Data ‘C’ Data ‘D’
Operation R/W R/W R/W R/W
Reset n/a n/a n/a n/a