Artesyn MVME5100, Programmer'S Reference Manual, Page: 128 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
128
LEND
Endian Select. If set, the PPC bus is operating in little endian mode. The PPC address is modified
as described in
When PPC Devices are Little Endian on page 98 . When LEND is clear, the PPC bus
is operating in Big Endian mode, and all data to/from PCI is swapped as described in When PPC
Devices are Big-Endian on page 97 .
PFBR
PCI Flush Before Read. If set, the PHB guarantees that all PPC initiated posted write transactions
are completed before any PCI initiated read transactions are allowed to complete. When PFBR
is clear, there is no correlation between these transaction types and their order of completion.
Refer to
Transaction Ordering for more information.
XMBH
PPC Master Bus Hog. If set, the PPC master of the PHB operates in the Bus Hog mode. Bus Hog
mode means the PPC Master continually requests the PPC bus for the entire duration of each
transfer. If Bus Hog is not enabled, the PPC master requests the bus in a normal manner. Refer
to the section
PPC Master for more information.
XFBR
PPC Flush Before Read. If set, the PHB will guarantee that all PCI initiated posted write
transactions will be completed before any PPC-initiated read transactions will be allowed to
complete. When XFBR is clear, there is no correlation between these transaction types and
their order of completion. Refer to the section titled
Transaction Ordering for more information.
XBTx
LEND PFBR HMBH XFBR XB
T1
XB
T0
P64 OP
IC
XID1 XID0
Operation
R/W R R R R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R R R R R R R
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Table 2-23 Revision ID Register (continued)
Address $FEFF0008
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31