Artesyn MVME5100, Programmer'S Reference Manual, Page: 198 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
198
3.2.3.5 Cache Coherency
The SMC supports cache coherency to SDRAM only. It does this by monitoring the ARTRY_
control signal on the PPC60x bus and behaving appropriately when it is asserted. When
ARTRY_ is asserted, if the access is a SDRAM read, the SMC does not source the data for that
access. If the access is a SDRAM write, the SMC does not write the data for that access.
Depending upon when the retry occurs, the SMC may cycle the SDRAM even though the data
transfer does not happen.
3.2.3.6 Cache Coherency Restrictions
The PPC60x GBL_ signal must not be asserted in the CSR areas.
3.2.3.7 L2 Cache Support
The SMC provides support for a look-aside L2 cache (only at 66.67 MHz) by implementing a
hold-off input, L2CLM_. On cycles that select the SMC, the SMC samples L2CLM_ on the second
rising edge of the CLK input after the assertion of TS_. If L2CLM_ is high, the SMC responds
normally to the cycle. If it is low, the SMC ignores the cycle.
3.2.4 SDRAM ECC
The SMC performs single-bit error correction and double-bit error detection for SDRAM across
64 bits of data using 8 check bits. No checking is provided for ROM/Flash.
The section discusses the following topics:

Cycle Types on page 198

Error Reporting on page 199

Error Logging on page 200
3.2.4.1 Cycle Types
To support ECC, the SMC always deals with SDRAM using full width (72-bit) accesses. When the
PPC60x bus master requests any size read of SDRAM, the SMC reads the full width at least once.
When the PPC60x bus master requests a four-beat write to SDRAM, the SMC writes all 72 bits
four times. When the PPC60x bus master requests a single-beat write to SDRAM, the SMC
performs a full width read cycle to SDRAM, merges in the appropriate PPC60x bus write data,
and writes full width back to SDRAM.