Artesyn MVME5100, Programmer'S Reference Manual, Page: 258 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
258
i2_datin
This bit is set whenever the I
2
C master controller has successfully received a byte of read data
from an I
2
C bus slave device. This bit is cleared after the I
2
C Receiver Data Register is read.
i2_err
This bit is set when both i2_start and i2_stop bits in the I
2
C Control Register are set at the same
time. The I
2
C master controller will then clear the contents of the I
2
C Control Register, and
further writes to the I
2
C Control Register will not be allowed until after the I
2
C Status Register
is read. A read from the I
2
C Status Register will clear this bit.
i2_ackin
This bit is set if the addressed slave device is acknowledged to either a start sequence or data
writes from the I
2
C master controller and cleared otherwise. The I
2
C master controller will
automatically clear this bit at the beginning of the next valid I
2
C operation.
i2_cmplt
This bit is set after the I
2
C master controller has successfully completed the requested I
2
C
operation and cleared at the beginning of every valid I
2
C operation. This bit is also set after
power-up.
3.3.3.21 I
2
C Transmitter Data Register
I2_DATAWR
Table 3-39 I
2
C Transmitter Data Register
Address $FEF800A8
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name I2_DATAWR
Operation READ ZERO READ ZERO READ ZERO READ/WRITE
Reset X X X 0 PL