Artesyn MVME5100, Programmer'S Reference Manual, Page: 85 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
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The PCI Slave fully supports the PCI lock function. From the perspective of the PPC bus, the PHB
enables a lock to a single 32 byte cache line. When a cache line has been locked, the PHB
snoops all transactions on the PPC bus. If a snoop hit happens, the PHB retries the transaction.
Note that the retry is ‘benign’ since there is no follow-on transaction after the retry is asserted.
The PHB continues to snoop and retry all accesses to the locked cache line until a valid ‘unlock’
is presented to the PHB and the last locked cache line transaction is successfully executed.
Note that the PHB locks the cache line that encompasses the actual address of the locked
transaction. For example, a locked access to offset 0x28 creates a lock on the cache line
starting at offset 0x20.
From the perspective of the PCI bus, the PCI Slave locks the entire resource. Any attempt by a
non-locking master to access any PCI resource represented by the PHB results in the PCI Slave
issuing a retry.
Parity
The PCI Slave supports address parity error detection, data parity generation, and data parity
error detection.
Cache Support
The PCI Slave does not participate in the PCI caching protocol.
2.3.3.3 PCI FIFO
A 64-bit by 16 entry FIFO (4 cache lines total) is used to hold data between the PCI Slave and the
PPC Master to ensure that optimum data throughput is maintained. The same FIFO is used for
both read and write transactions. A 52-bit by 4 entry FIFO is used to hold command information
being passed between the PCI Slave and the PPC Master. If write posting is enabled, then the
maximum number of transactions that may be posted is limited by the abilities of either the
data FIFO or the command FIFO. For example, one burst transaction, 16 double words long,
would make the data FIFO the limiting factor for write posting. Four single beat transactions
would make the command FIFO be the limiting factor. If either limit is exceeded then any
pending PCI transactions are delayed (TRDY_ is not asserted) until the PPC Master has
completed a portion of the previously posted transactions and created some room within the
command and/or data FIFOs.