Artesyn MVME5100, Programmer'S Reference Manual, Page: 208 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
208
3.2.6 I
2
C Interface
The ASIC has an I
2
C (Inter-Integrated Circuit) two-wire serial interface bus: Serial Clock Line
(SCL) and Serial Data Line (SDA). This interface has master-only capability and may be used to
communicate the configuration information to a slave I
2
C device such as serial EEPROM. The
I
2
C interface is compatible with these devices, and the inclusion of a serial EEPROM in the
memory subsystem may be desirable. The EEPROM could maintain the configuration
The information in Table 2-6 applies to access timing when configured for devices with an
access time equal to 5 clock periods.
Table 3-8 PPC60x Bus to ROM/Flash Access Timing (30ns @ 100 MHz)
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
16
Bits
64
Bits 16
Bits
64
Bits 16
Bits
64
Bits 16
Bits
64
Bits 16
Bits
64
Bits
4-Beat Read 34 13 28 7 28 7 28 7 118 34
4-Beat Write N/A N/A
1-Beat Read (1 byte) 13 13 - - - - - - 13 13
1-Beat Read (2 to 8
bytes) 34 13 - - - - - - 34 13
1-Beat Write 21 21 - - - - - - 21 21
The information in Table 2-7 applies to access timing when configured for devices with an
access time equal to 5 clock periods.