Artesyn MVME5100, Programmer'S Reference Manual, Page: 112 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
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2.4.6 Processor’s Current Task Priority
Each processor has a task priority register which is set by system software to indicate the
relative importance of the task running on that processor. The processor will not receive
interrupts with a priority level equal to or lower than its current task priority. Therefore, setting
the current task priority to 15 prohibits the delivery of all interrupts to the associated
processor.
2.4.7 Nesting of Interrupt Events
A processor is guaranteed never to have an in service interrupt preempted by an equal or lower
priority source. An interrupt is considered to be in service from the time its vector is returned
during an interrupt acknowledge cycle until an EOI (End of Interrupt) is received for that
interrupt. The EOI cycle indicates the end of processing for the highest priority in service
interrupt.
2.4.8 Spurious Vector Generation
Under certain circumstances the MPIC will not have a valid vector to return to the processor
during an interrupt acknowledge cycle. In these cases the spurious vector from the spurious
vector register will be returned. The following cases would cause a spurious vector fetch:

INT is asserted in response to an externally sourced interrupt, which is activated with level
sensitive logic, and the asserted level is negated before the interrupt is acknowledged.

INT is asserted for an interrupt source, which is masked using the mask bit, in the Vector-
Priority register before the interrupt is acknowledged.
2.4.9 Interprocessor Interrupts (IPI)
Processors 0 and 1 can generate interrupts which are targeted for the other or both processors.
There are four Interprocessor Interrupts (IPI) channels. The interrupts are initiated by writing a
bit in the IPI dispatch registers. If subsequent IPI’s are initiated before the first is acknowledged,
only one IPI will be generated. The IPI channels deliver interrupts in Direct Mode and can be
directed to more than one processor.