Artesyn MVME5100, Programmer'S Reference Manual, Page: 32 / 318

Product Data and Memory Maps
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
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1.2.1.4 VME Memory Map
The MVME5100 is fully capable of supporting both the PREP and the CHRP VME Memory Maps
with RAM size limited to 2 GB. The default values for the VME Slave Image registers are listed in
Chapter 3, PPCBug, of the MVME5100 Single Board Computer Installation and Use manual.
1.2.2 PCI Local Bus Memory Map
The PCI memory map is controlled by the MPU/PCI bus bridge controller portion of the Hawk
ASIC and by the Universe PCI/VME bus bridge ASIC. The Hawk and Universe devices adjust
system mapping to suit a given application via programmable map decoder registers.
No default PCI memory map exists. Resetting the system turns the PCI map decoders off, and
they must be reprogrammed in software for the intended application.
For detailed PCI memory maps, including suggested CHRP- and PREPcompatible memory
maps, refer to the Hawk portion of this manual (
Chapter 2, Hawk PCI Host Bridge & Multi-
Processor Interrupt Controller and Chapter 3, System Memory Controller (SMC) ).
1.2.3 VMEbus Memory Map
The map of the VMEbus is programmable. Like other parts of the MVME510x memory map, the
mapping of local resources as viewed by VMEbus masters varies among applications.
The Universe PCI/VME bus bridge ASIC includes a user-programmable map decoder for the
VMEbus-to-local-bus interface. The address translation capabilities of the Universe enable the
processor to access any range of addresses on the VMEbus.
Recommendations for VMEbus mapping, including suggested CHRP- and PREP-compatible
memory maps, can be found in the Hawk portion of this manual (
Chapter 2, Hawk PCI Host
Bridge & Multi-Processor Interrupt Controller and Chapter 3, System Memory Controller (SMC) ).
1.3 System Bus
The following sections describe the processor system bus for the MVME5100. Only the PPC60x
bus interface is supported.