Artesyn MVME5100, Programmer'S Reference Manual, Page: 63 / 318

Chapter 2
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
63
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2.1 Overview
This chapter describes the architecture and usage of the PowerPC to PCI Host Bridge (PHB) and
the Multi-Processor Interrupt Controller (MPIC) portion of the Hawk ASIC. The Hawk is
intended to provide PowerPC 60x (PPC60x bus) compliant devices access to devices residing on
the PCI Local Bus. In the remainder of this chapter, the PPC60x bus is referred to as the PPC bus
and the PCI Local Bus as PCI. PCI is a high performance 32-bit or 64-bit burst mode,
synchronous bus capable of transfer rates of 132 MB/sec in 32-bit mode or 264 MB/sec in 64-
bit mode using a 33 MHz clock.
The chapter discusses the following topics:

Block Diagram

Functional Description

Multi-Processor Interrupt Controller (MPIC)

Registers
2.1.1 Features
The following table discusses the features of Hawk PCI Host Bridge & Multi-Processor Interrupt
Controller:
Table 2-1 2Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Feature Description
PPC Bus Interface  Direct interface to MPC750, MPC755, or MPC7410 processor
 64-bit data bus, 32-bit address bus
 Four independent software programmable slave map decoders
 Multi-level write post FIFO for writes to PCI
 Support for PPC bus clock speeds up to 100 MHz
 Selectable big or little endian operation
 3.3 V signal levels