Artesyn MVME5100, Programmer'S Reference Manual, Page: 222 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
222
3.2.6.5 I
2
C Sequential Read
The I
2
C sequential read can be initiated by either an I
2
C random read (described here) or an I
2
C
current address read. The first step in the programming sequence of an I
2
C random read
initiation is to test the i2_cmplt bit for the operation-complete status. The next step is to
initiate a start sequence by first setting the i2_start and i2_enbl bits in the I
2
C Control Register
and then writing the device address (bits 7-1) and write bit (bit 0=0) to the I
2
C Transmitter Data
Register. The i2_cmplt bit is automatically cleared with the write cycle to the I
2
C Transmitter
Data Register. The I
2
C Status Register must now be polled to test the i2_cmplt and i2_ackin
bits. The i2_cmplt bit becomes set when the device address and write bit are transmitted, and
the i2_ackin bit provides status as to whether or not a slave device acknowledged the device
address. With the successful transmission of the device address, the initial word address is
loaded into the I
2
C Transmitter Data Register to be transmitted to the slave device. Again,
i2_cmplt and i2_ackin bits must be tested for proper response. At this point, the slave device is
still in a write mode. Therefore, another start sequence must be sent to the slave to change the
mode to read by first setting the i2_start, i2_ackout, and i2_enbl bits in the I
2
C Control
Register and then writing the device address (bits 7-1) and read bit (bit 0=1) to the I
2
C
Transmitter Data Register. After i2_cmplt and i2_ackin bits are tested for proper response, the
I
2
C master controller writes a dummy value (data=don’t care) to the I
2
C Transmitter Data
Register.This causes the I
2
C master controller to initiate a read transmission from the slave
device. After the I
2
C master controller has received a byte of data (indicated by i2_datin=1 in
the I
2
C Status Register) and the i2_cmplt bit has also been tested for proper status, the I
2
C
master controller responds with an acknowledge and the system software may then read the
data by polling the I
2
C Receiver Data Register.
As long as the slave device receives an acknowledge, it will continue to increment the word
address and serially clock out sequential data words. The I
2
C sequential read operation is
terminated when the I
2
C master controller does not respond with an acknowledge. This can be
accomplished by setting only the i2_enbl bit in the I
2
C Control Register before receiving the
last data word. A stop sequence then must be transmitted to the slave device by first setting
the i2_stop and i2_enbl bits in the I
2
C Control Register and then writing a dummy data