Artesyn MVME5100, Programmer'S Reference Manual, Page: 82 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
82
MPIC Control Registers
The MPIC control registers are located within either PCI Memory or PCI I/O space using
traditional PCI defined base registers within the predefined 64-byte header. Refer to
Multi-
Processor Interrupt Controller (MPIC) for more information.
2.3.3.2 PCI Slave
The PCI Slave provides the control logic needed to interface the PCI bus to the PCI FIFO. The PCI
Slave can accept either 32-bit or 64-bit transactions; however, it can only accept 32-bit
addressing. There is no limit to the length of the transfer that the PCI Slave can handle. During
posted write cycles, the PCI Slave will continue to accept write data until the PCI FIFO is full. If
the PCI FIFO is full, the PCI Slave will hold off the master with wait states until there is more
room in the FIFO. The PCI Slave will not initiate a disconnect. If the write transaction is
compelled, the PCI Slave will hold off the master with wait states while each beat of data is
being transferred. The PCI Slave issues TRDY_ only after the data transfer has successfully
completed on the PPC bus. If a read transaction is being performed within an address space
marked for prefetching, the PCI Slave (in conjunction with the PPC Master) attempts to read
ahead far enough on the PPC bus to allow for an uninterrupted burst transaction on the PCI
bus. Read transactions within address spaces marked for no prefetching receive a TRDY_
indication on the PCI bus only after one burst read has successfully completed on the PPC bus.
Each read on the PPC bus is only started after the previous read is acknowledged on the PCI bus
and there is an indication that the PCI Master wishes for more data to be transferred.
The following paragraphs identify some associations between the operation of the PCI slave
and the PCI 2.1 Local Bus Specification requirements.
Command Types:
The following table shows which types of PCI cycles the slave has been designed to accept:
Table 2-8 PCI Slave Response Command Types
Command Type Slave Response?
Interrupt Acknowledge No
Special Cycle No
I/O Read Yes
I/O Write Yes