20-1
20 Block Diagram
Select
MAIN
CPU
Program
Memory
(Flash)
Buffer
Manager
and DMA
(CPU)
Bar Meter
CTL
Clock GEN
Mixer
Buffer Memory
(FIFO Memory)
AC/DC
CHG
BATT
Analog CPU
DSP for
Calib-
ration
Display
Keys
EXT
CTL
Remocon
RS-232C
SYNC
RTC
SCSI
CTL
SDX Drive
DC
DC/DC
CH-1 ANALOG OUTPUT
CH-1 ANALOG INPUT
AUX-2 (IRIG-B)
IRIG
Decoder
AUX-1 (DIGITAL)
Serial
I/F
Serial
I/F
PWR CPU
A/D
D/A
SCSI
Emulation/Transfer
Board
Channel
Expansion/Bit Stream
/MPEG VIDEO
Board
CH-8 ANALOG INPUT
CH-8 ANALOG OUTPUT
AMP
A/D
D/A
AMP
MIC
ATT
AMP
Deci. DF
Interp.
DF
Analog
LPF
Analog
LPF
ATT
AMP
Analog
LPF
Analog
LPF
Deci. DF
Interp.
DF
Oversampling
AD
Oversampling
AD
Oversampling
AD
Oversampling
AD
TRIG/REC IN
PLL
CHD1 LSB DIGITAL I/O
CHD4 LSB DIGITAL I/O
PHONE
AC
OPTION SLOT 2
OPTION SLOT 1