GE LPS-D, Инструкция по эксплуатации

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LPS-D Line Protection System GE Power Management
13.2 DESIGN CONSIDERATIONS 13 XPRESSION BUILDER
13
13.2 DESIGN CONSIDERATIONS 13.2.1 OVERVIEW
Xpression Builder logic is processed every other millisecond. This should be considered when designing logic
to implement in the relay. The more gates connected in series, the longer the time delay from the initial logic
input to the final logic output (roughly 2 ms per gate) of the expected result. This delay applies to the Xpression
Builder logic only. The scheme logic outputs of the relay will not be delayed with the use of configurable logic.
Figure 13–1: LOGIC PROCESSING DELAY
For example, the TRIP (flag #33) output of the scheme logic, when directly connected to an output contact, will
close that contact when it becomes high (logic 1) with no additional processing delay as shown in part A of the
figure above. If the TRIP flag is connected to a Boolean gate before it reaches an output contact, a gate pro-
cessing delay of 2 ms should be added to the expected function operating time as shown in part B above. This
should be taken into consideration in the design of the relay configurable logic. This is why it is recommended
all user defined logic be tested in a laboratory environment before installation in the field. This will ensure user
confidence and expected performance of the configurable logic developed with the relay internal flags.
13.2.2 BOOLEAN OPERATORS, LATCHES, TIMERS, & COUNTERS
a) BOOLEAN OPERATORS
The operation of the Boolean operators (AND, OR, and NOT) are self explanatory. Each gate may have up to
four (4) inputs. Each of the inputs may be logically inverted by clicking the right mouse button when the cursor
is at the input of the gate. A small circle at the gate input will indicate the inversion of the input signal. The out-
put can also be inverted by clicking the right mouse button when the cursor is at the output of the gate. A small
circle at the gate output will indicate the inversion of the output signal.
b) LATCHES
A “D” flip-flop is used in the Xpression Builder logic as shown in Figure 13–2: LATCH AND TRUTH TABLE. The
D input is where the data bit to be stored is applied. The T or clock input controls the flip-flop. It determines
whether the data on the D input line is recognized (clocked) or ignored. If the T input line is high (binary 1), the
data on the D input line is stored in the flip-flop. If the T input line is low (binary 0), the D input line is not recog-
nized. The Q output line directly reflects the state of the flip-flop. If the flip-flop is set, then Q equals a high
(binary 1). If Q equals a low (binary 0), then the flip-flop is reset.
PU ~ 2 ms
DO ~ 2 ms
(A)
(B)
Trip
T 1
(A)
Trip
T 1
(B)
input always low (logic 0)
P U
D O
Trip Trip
T1
T1