Tadpole SPARCbook 3 series, Reference Manual

Page: 215 / 216

Index-v
connecting devices 5-2
SCSI controller 1-10, 5-1
configuration registers 5-6
DMA registers 5-7
DMA support 5-7
FIFO/flags register 5-6
interrupt status register 5-5
interrupts 5-7
select/reconnect register 5-6
sequence step register 5-6
status register 5-5
synchronous transfer period register 5-6
transfer count registers 5-6
SCSI controller, command registers 5-3
select/reconnect registers,SCSI 5-6
sequence step registers,SCSI 5-6
serial communications controllers 4-1
serial interface
architecture 4-1
channel assignment 4-2
handshakes 4-10
overview 1-9
SIMMs, DRAM 1-8
SLAVIO
address space 3-2
configuration control 3-9
configuration register 3-9
counter-timer 1-9
interrupt registers 3-7
interrupts 3-6
memory map 3-4
serial channel registers 4-3
serial communications controllers 4-1
SLAVIO expansion interface, TS102 7-6
SLAVIO, general description 3-3
slow I/O subsystem, overview 1-9
SPARCbook 3 address map 3-2
status and control registers
Power 9100 11-8
status registers, SCSI 5-5
SVGA unit 11-7
synchronization, display 11-4
synchronous transfer period register, SCSI 5-6
system architecture 1-1
system bus architecture 1-6
system control registers, Power 9100 11-9
T
time slots, ISDN 8-6
TLB entry fields 2-9
transfer count registers,SCSI 5-6
translation lookaside buffer 2-9
TS102
architecture overview 7-2
card interrupt registers 7-8
card status registers 7-9
generic chip select decoding 7-6
memory map 7-4
microcontroller interface 7-3
registers 7-7
SLAVIO expansion interface 7-6
TTY ports
pinout B-6
TurboSPARC 1-5
typographical conventions xi
V
video connector B-4
video control registers 11-12
VRAM control registers 11-15
W
window registers 2-6
word, definition xi
S3GX_TRMBook Page v Friday, September 19, 1997 11:39 am