Tadpole SPARCbook 3 series, Reference Manual

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1-6
Architecture Overview
Main System Buses
1.5 Main System Buses
The SPARCbook 3 architecture is based around three main buses
conventional for SPARC-based workstations. These are the Memory bus
which connects the CPU to the main memory; the SBus which connects the
CPU to the major I/O devices; and the EBus.
1.5.1 Memory bus
The microSPARC II’s integral memory controller is connected to the
system DRAM directly via a 64 bit high speed memory bus. The
microSPARC II provides direct addressing and control for the main
memory, illustrated in Figure 1-3, providing the write enable signal and
RAS and CAS lines. The smallest data movement is 64 bits; smaller
transfers are carried out by using read-modify-write operations. Parity
protection is provided by the CPU as 1 bit per word (32 bits) of data. SBus
based master I/O devices are able to access the memory bus via the
processor’s SBus interface.
1.5.2 SBus
The microSPARC II incorporates a complete SBus controller. The SBus
connects the microSPARC II to the Weitek P9100 graphics controller,
NCR89C105 SLAVIO, NCR89C100 MACIO and T725FC ISDN
controller. See Figure 1-4.
Figure 1-3 Main Memory/CPU Interface
12
64
Data
Address
Control
STSX1012
microSPARC II
DRAM
S3GX_TRMBook Page 6 Friday, September 19, 1997 11:39 am