Tadpole SPARCbook 3 series, Reference Manual

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Architecture Overview
1-7
Main System Buses
The microSPARC II provides an SBus Master and Slave interface which
enables the I/O devices with integrated DMA capability to gain access to
the main memory without encroaching unduly on processor bandwidth.
SBus master and slave operations can be single cycle or bursts, and
dynamic bus sizing is supported (for single-cycle transfers). Master
accesses by the microSPARC II to the SBus cannot be cached, and only
double burst accesses are supported.
1.5.3 Ebus
The third system bus within the SPARCbook 3 is the Ebus. This is an 8-bit
data bus driven by the SLAVIO. The SLAVIO divides the EBus address
space into a number of regions by providing address generated EPROM,
RTC/RAM and Generic chip select signals. The EBus interface of the
SLAVIO is limited to a data bus and the chip select signals. The EBus
address bus is driven by the TS102 ASIC to enable the CPU to gain access
to the internal registers of devices on the EBus. Figure 1-5 provides a
simplified illustration of the EBus architecture.
Figure 1-4 SBus Connected Devices
STSX1012
microSPARC II
Weitek P9100
Graphics Controller
NCR89C105
SLAVIO
TS102
PCMCIA Controller
NCR89C100
MACIO
Data
Address
32 32 32 16
T725FC
ISDN Controller
32
S3GX_TRMBook Page 7 Friday, September 19, 1997 11:39 am