Tadpole SPARCbook 3 series, Reference Manual

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The SPARC CPU
2-3
Integer Unit
The SPARC CPU is a RISC (reduced instruction set computer) based
processor which uses a simplified command set to carry out operations. It
is able to execute most instructions within a single clock cycle.
The high performance of the SPARC CPU is enhanced by the ability of the
floating point unit (FPU) to execute instructions simultaneously with the
integer unit (IU), and by the provision of cache memory. The cache
memory is a specialized area of fast (zero wait state) memory which allows
many instructions and operands to be fetched locally by the CPU without it
having to access the (comparatively slow) main memory.
2.2 Integer Unit
The IU is the main processing engine, executing all instruction groups
except for floating point operations.
2.2.1 Pipeline
The SPA IU has a five-stage pipeline, receiving instructions which
complete five cycles later. The five stages are fetch, decode, execute, cache
access and write back. These stages are overlapped to allow a peak
execution rate of one instruction per cycle.
The one instruction per cycle performance is supported by the IU’s 32-bit
data bus which interfaces directly with the instruction cache. If an
instruction is in the cache, it is returned in the same cycle in which it was
requested.
2.2.2 Instruction set overview
The integer instructions supported by the micro SPARC processor fall into
the following basic categories:
• Load and Store Instructions
• Arithmetic, Logical and Shift Instructions
• Control Transfer Instructions
• Read/Write Control Registers Instructions.
The load and store instructions are the only instructions that cause the
movement of data on the memory interface. They use two registers or a
register and a constant to calculate the memory address involved. Halfword
accesses must be aligned on 2-byte boundaries, word accesses on 4-byte
boundaries, and doubleword accesses on 8-byte boundaries. These
alignment restrictions greatly speed up memory access.
S3GX_TRMBook Page 3 Friday, September 19, 1997 11:39 am