Tadpole SPARCbook 3 series, Reference Manual

Page: 100 / 216

8-4
ISDN and 16-bit Audio
DBRI Overview
8.2.4 DBRI Programming Model
This section gives a brief overview of the DBRI programming interface. It
is not, however, intended to provide a detailed programming guide.
The DBRI operates as a coprocessor, maintaining its own data structures in
memory and operating on its own instruction set. The host assembles lists
of instructions, services interrupts and maintains receive and transmit data
buffers in main memory. The DBRI accesses memory using DMA
operations.
The DBRI can be configured to select time slots and route selected data
between the three serial interfaces and the SBus. It can be dynamically
reconfigured to provide different routing strategies for different operations.
For example, audio data carried on one B channel from the TE interface
could be routed through the CHI for audio output, while data on the other
B channel could be routed to the SBus interface for DMA into main
memory. Figure 8-3 shows this configuration
Data Pipes The DBRI provides 32 data pipes through which data is channelled
between the interfaces. These are divided into two types: sixteen long data
pipes, so called because they have enough depth to buffer data for DMA (80
bytes); and sixteen short data pipes of 32 bits each. The long data pipes can
be used for DMA with optional HDLC formatting in either direction. The
short data pipes are used for data transfer between two serial interfaces
(CHI, NT, and TE) and can have time slots assigned to both ends.
Figure 8-3 Long and Short Pipes
Long Pipe
Short Pipe
B1 Slots
B2 Slots
From TE
To CHI for Audio Output
DMA to Memory
S3GX_TRMBook Page 4 Friday, September 19, 1997 11:39 am