Tadpole SPARCbook 3 series, Reference Manual

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Architecture Overview
1-5
Processor
1.4 Processor
The CPU used in the S3TX is the TurboSPARC and the CPU used in the
S3XPand S3GX is the microSPARC II.
The TurboSPARC CPU provides the following key features:
• SPARC compliant V8 Integer Unit core
• SPARC Reference Memory Management Unit
• Floating Point ALU
• FP-Muliply Unit
• FP Divide/Square Root Unit
• 16 Kbyte Instruction Cache
• 16 Kbyte Data Cache
• Secondary Cache Controller
• DRAM Controller
• SBus Controller, Master and Slave Interface.
The TurboSPARC implemented in the S3TX operates at 170 MHz and
provides performance figures of 3.5 SPECint95 and 3.0 SPECfp95.
The microSPARC II CPU provides the following key features:
• SPARC-II compliant V8 Integer Unit (IU) core
• SPARC Reference Memory Management Unit (MMU)
• MEIKO Floating Point Unit (FPU)
• 16 Kbyte Instruction Cache
• 8 Kbyte Data Cache
• Memory Controller
• SBus Controller, Master & Slave Interface.
The microSPARC II implemented in the SPARCbook 3XP processor
operates at 85 MHz and provides performance figures of 64 SPECint92 and
54.6 SPECfp92.
The microSPARC II implemented in the SPARCbook 3GX processor
operates at 105 MHz and provides performance figures of 64 SPECint92
and 54.6 SPECfp92.
S3GX_TRMBook Page 5 Friday, September 19, 1997 11:39 am