Ethernet Interface
6-3
LAN Controller Registers
6.2
LAN Controller Registers
Access to the LAN controller’s internal registers is gained via two 16-bit
locations, the Register Data Port (RDP) and Register Address Port (RAP).
The RAP is loaded with an index to the required register, and then the
register data can be read from or written to the RDP.
6.2.1
Register Indexing
The lower 2 bits in the Register Address Port are used to index the internal
Control and Status Registers. The remaining bits, D(15:2) are reserved. The
encoding of D(1:0) is shown in Table 6-2.
6.2.2
Control and Status Register 0
This register contains control, status, error and interrupt information.
Address
Register
Size
Access
0x78C00000
Register Data Port (RDP)
16-bit
R/W
0x78C00002
Register Address Port (RAP)
16-bit
R/W
Table 6-1 LAN Controller Register Locations
Bit 1
Bit 0
Register
0
0
Control and Status Register 0
0
1
Control and Status Register 1
1
0
Control and Status Register 2
1
1
Control and Status Register 3
Table 6-2 Register Indexing
Figure 6-2 Control and Status Register 0
15
0
ERR BAB CE MISS ME RINT TINT IFIN IEN RON TON TD STP STR INIT
S3GX_TRMBook Page 3 Friday, September 19, 1997 11:39 am
Summary of Contents for SPARCbook 3 series
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Page 44: ...2 16 The SPARC CPU SBus Controller S3GX_TRMBook Page 16 Friday September 19 1997 11 39 am...
Page 76: ...5 8 SCSI Controller DMA Support S3GX_TRMBook Page 8 Friday September 19 1997 11 39 am...
Page 146: ...9 28 MODEM Class 2 Fax Command Set S3GX_TRMBook Page 28 Friday September 19 1997 11 39 am...
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