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Tadpole SPARCbook 3 series, Reference Manual

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8-14

ISDN and 16-bit Audio

Audio CODEC

8.3

Audio CODEC

A Crystal Semiconductor Corporation CS4215 Multimedia Audio 
Coder-Decoder (CODEC) provides the SPARCbook 3 with stereo audio 
capabilities. It operates in conjunction with the DBRI with which it is 
connected via a synchronous serial link. The DBRI’s concentration 
highway interface (CHI) provides a specialized serial interface which is 
used to support the audio codec’s operations. Figure 8-5 shows how the 
DBRI and audio codec are connected.

8.3.1

Clocking and Data Synchronization

The SPARCbook 3 implementation of the DBRI and audio codec provides 
flexible operation of the audio interface. The codec has two clock inputs, as 
illustrated in Figure 8-6, which are used to generate a sampling clock for 
the internal analog-to-digital and digital-to-analog converters and can be 
programmed supply serial port timing. The codec is able to function as a 
timing master or timing slave for serial transfers between at it and the 
DBRI. It can generate frame synchronization and serial data clocks or can 
receive them from the DBRI. 

The audio CODEC is not supplied with a clock on its CLKIN pin.

The CODEC operates in two modes: control mode, during which command 
and status information are transferred; and data mode, during which audio 
data is transferred. The operating mode is controlled via one if the DBRI’s 
bit I/O pins. 

Figure 8-5   DBRI and CODEC Interface

CHI

Serial Clock

Frame Sync

Serial Data

Serial Data

PIO3

PIO2

PIO1

CODEC

D/C

RESET

PDN

DBRI

S3GX_TRMBook  Page 14  Friday, September 19, 1997  11:39 am

Summary of Contents for SPARCbook 3 series

Page 1: ...Series Technical Reference Manual 980327 02 3 S3GX_TRMBook Page i Friday September 19 1997 11 39 am...

Page 2: ...rks of UNIX Systems Laboratories Inc All other product names mentioned herein are the trademarks of their respective owners All SPARC trademarks including the SCD Compliant Logo are trademarks or regi...

Page 3: ...in System Buses 1 6 1 5 1 Memory bus 1 6 1 5 2 SBus 1 6 1 5 3 Ebus 1 7 1 6 DRAM 1 8 1 7 Slow I O Subsystem 1 9 1 7 1 Serial Channels 1 9 1 7 2 Counter Timers 1 9 1 7 3 Interrupt Controller 1 10 1 7 4...

Page 4: ...5 Memory Interface 2 14 2 6 Instruction Cache 2 14 2 7 Data Cache 2 14 2 8 SBus Controller 2 14 2 8 1 Programmed I O 2 15 2 8 2 DVMA 2 15 Chapter 3 Memory Map and Interrupts 3 1 Address Map 3 2 3 1 1...

Page 5: ...Operations 6 5 Chapter 7 PCMCIA Interface 7 1 TS102 Architecture Overview 7 2 7 1 1 SBus interface 7 2 7 1 2 PCMCIA interface 7 3 7 1 3 Microcontroller interface 7 3 7 2 TS102 Memory Mapping 7 4 7 2...

Page 6: ...Parallel Port Overview 10 2 10 1 1 Parallel Port DMA Operations 10 2 10 2 Parallel Port Control Registers 10 3 Chapter 11 Display Interface 11 1 Display Interface Overview 11 2 11 1 1 Architecture 11...

Page 7: ...Modify Commands 12 11 12 2 4 Commands Returning no Status 12 14 12 2 5 Block Transfer Commands 12 15 12 2 6 Generic Commands 12 16 12 2 7 Generic Commands with Optional Status 12 17 12 2 8 Administrat...

Page 8: ...viii S3GX_TRMBook Page viii Friday September 19 1997 11 39 am...

Page 9: ...t is assumed that you are familiar with the operation of SPARCbook 3 as detailed in the SPARCbook 3 User Guide and that you have an understanding of computer hardware Note The SPARCbook 3 Technical Re...

Page 10: ...ns discusses the SCSI controller Chapter 6 Ethernet Interface discusses the Ethernet interface of the SPARCbook 3 Chapter 7 PCMCIA discusses the PCMCIA interface implemented in the SPARCbook 3 Chapter...

Page 11: ...ntain 32 bits A doubleword is taken to contain 64 bits Typographical conventions Different typography is used in this guide to distinguish between normal text examples of SPARCbook responses and cases...

Page 12: ...ughout this manual to explain items of related interest to the topic under discussion and are used to refer the reader to another part of the manual or to other documentation Note This is an example o...

Page 13: ...sses the architecture of the SPARCbook 3 It describes the main system components and how they are packaged together to deliver workstation class performance in a compact notebook form factor S3GX_TRMB...

Page 14: ...s all of the I O components together with the display controller RAMDAC and 2MB of Video RAM and the battery management hardware It is populated on both sides using mainly surface mount devices in ord...

Page 15: ...d within the system s lid along with an inverter board required to drive the display s backlight Systems use either 9 4 inch 640 x 480 or 10 4 inch 800 x 600 color TFT display to provide a sharp image...

Page 16: ...ARCbook 3 Architecture 64 Memory Bus MACIO SLAVIO TS102 ASIC Microcontroller Subsystem ISDN Audio Graphics Controller RAMDAC 2x PCMCIA Sockets Serial Ext Keyboard Mouse Ethernet Parallel ISDN Audio Ex...

Page 17: ...X operates at 170 MHz and provides performance figures of 3 5 SPECint95 and 3 0 SPECfp95 The microSPARC II CPU provides the following key features SPARC II compliant V8 Integer Unit IU core SPARC Refe...

Page 18: ...strated in Figure 1 3 providing the write enable signal and RAS and CAS lines The smallest data movement is 64 bits smaller transfers are carried out by using read modify write operations Parity prote...

Page 19: ...is the Ebus This is an 8 bit data bus driven by the SLAVIO The SLAVIO divides the EBus address space into a number of regions by providing address generated EPROM RTC RAM and Generic chip select signa...

Page 20: ...e SIMMs are each 33 bits wide 32 bits data and 1 bit parity and are available in sizes of 8Mbytes x 33 16Mbytes x 33 32Mbytes x 33 and 64Mbytesx33 This gives a usable memory capacity of up to of 128 T...

Page 21: ...IN connectors which are marked as Serial Channel A and Serial Channel B on the I O panel at the rear of the SPARCbook 3 system unit The two remaining serial channels provide the keyboard and mouse int...

Page 22: ...ast I O Subsystem The Fast I O Subsystem includes the SCSI parallel and network interfaces These are controlled by the NCR89C105 MACIO This device is a custom ASIC designed to be operated with the NCR...

Page 23: ...t Interface For information about the connections refer to Appendix B Connector Information 1 8 3 Parallel Port The parallel port breakout cable supplied with the SPARCbook enables connection to a bi...

Page 24: ...nals Video timing control up to 165MHz 2D Graphics Accelerator Supports X window drawing mode Powerful graphics primitives The Weitek Power 9100 User Interface Controller provides programmable display...

Page 25: ...h allows adjustment of the RTC function in 2ppm steps The device is accessed via the EBus port of the SLAVIO device 1 11 ISDN and 16 Bit Audio Controller The ISDN and Audio interface consists of two m...

Page 26: ...res Stereo analog to digital and digital to analog conversion 4KHz to 48KHz sample rates 16 bit linear and 8 bit u law or A law coding Serial digital interface compatible with AT T CHI Concentration H...

Page 27: ...stem provides system housekeeping support freeing the main CPU A Hitachi H8 337 microcontroller is used offering the following features The microcontroller subsystem performs the following functions I...

Page 28: ...1 16 Architecture Overview Microcontroller Subsystem S3GX_TRMBook Page 16 Friday September 19 1997 11 39 am...

Page 29: ...rocessors In the case of he S3XP and S3GX microSPARC II is used in the case of the S3TX TurboSPARC is used This chapter provides a general overview of SPARC CPU For further information please refer to...

Page 30: ...e Instruction Cache 8 or 16 Kbyte Data Cache Memory Controller SBus Controller Master and Slave Interface Figure 2 1 MicroSPARC II Architecture Integer Floating Point Instruction Cache Data Cache Writ...

Page 31: ...h decode execute cache access and write back These stages are overlapped to allow a peak execution rate of one instruction per cycle The one instruction per cycle performance is supported by the IU s...

Page 32: ...write the contents of various control registers Generally the source or destination is implied by the instruction 2 2 3 Traps and interrupts The SPARC design supports a full set of traps and interrup...

Page 33: ...the state of the machine with respect to its peripherals 2 2 5 IU internal registers The IU contains working registers or r registers and control registers The r registers are used for storage by pro...

Page 34: ...valid window is caused by an instruction 2 2 6 IU control registers These include the Processor Status Register the Window Invalid Mask Register the Trap Base Register the Y Register and the Program C...

Page 35: ...FPU contains a 32x32 bit register file INSTRUCTION MIN TYP MAX fads 4 4 17 faddd 4 4 17 fsubs 4 4 17 fsubd 4 4 17 fmuls 5 5 25 fmuld 7 9 32 fdivs 6 20 38 fdivd 6 35 56 fsqrts 6 37 51 fsqrtd 6 65 80 f...

Page 36: ...ile the FPU supplies or receives the data Although the FPU operates concurrently with the IU a program containing floating point computations generates results as if the instructions were being execut...

Page 37: ...entry represent the decoded ACC bits from the matching PTE These are User Rd Wr Ex and Supervisor Rd Wr Ex Level This 3 bit field is used to allow the proper tag match of region and segment PTEs I O...

Page 38: ...Bit 5 Always 1 for a PTE in the TLB For a PTE in physical memory this bit is set when the page is accessed Bits 4 2 ACC Access Permissions This field indicates whether access is permitted for the tra...

Page 39: ...the I OPTE is valid Bit 0 This bit is to be written as zero WAZ in the Memory I O Page Table by software 2 4 2 Address translation During an access by the IU the virtual address supplied by the IU an...

Page 40: ...bles the search continues to the next lower level If a page table entry PTE is found the search is terminated and the entry is stored in the TLB If no PTE is found at all a synchronous fault exception...

Page 41: ...es three page table levels is shown in the illustration in Figure 2 5 In this example A 31 12 from the virtual address are used to index the page tables and A 11 0 supply an offset address into the se...

Page 42: ...anized as 512 lines of 32 bytes each 2 7 Data Cache The data cache is a 8Kbyte direct mapped physically tagged write through cache with no write allocate It is organized as 512 lines of 16 bytes each...

Page 43: ...ms write posting during processor writes allowing processing to continue while the SBus transaction is completed During reads processing is stalled until the data becomes valid at the end of the SBus...

Page 44: ...2 16 The SPARC CPU SBus Controller S3GX_TRMBook Page 16 Friday September 19 1997 11 39 am...

Page 45: ...d interrupt architecture of SPARCbook 3 The SLAVIO incorporates an interrupt controller and is used to coordinate all on board interrupts These include interrupts from devices on the board and interru...

Page 46: ...for the Ethernet parallel and SCSI interfaces including FIFO support and allow burst transfers to be performed on the SBus Connected to the SLAVIO but isolated from the SBus are the Boot ROM the O S R...

Page 47: ...internal interface devices each present an independent interface to the host Details of these control interfaces are provided in the relevant chapter for each interface Within their assigned spaces in...

Page 48: ...f Audio and Auxiliary Port Byte 1302000 1303FFF Auxiliary Control Status Port Byte 1300000 1301FFF Audio Device Byte 1204000 12FFFFF Echoes of RTC RAM and Diagnostic LEDS Byte Halfword Word 1202000 12...

Page 49: ...3 are signaled to the microSPARC as a 4 bit priority encoded value on S_IRL 3 0 Control of interrupts and prioritization is carried out by the SLAVIO The microSPARC provides a structure of traps whic...

Page 50: ...ides a summary of the interrupt request sources within SPARCbook 3 Level Source SLAVIO MACIO SBus 0 No Interrupts Pending 1 SOFTINT 1 2 SOFTINT 2 IRQ1 3 SOFTINT 3 Parallel Port IRQ2 4 SOFTINT 4 SCSI 5...

Page 51: ...R 71E00004 Processor Clear Pending W 71E00008 Processor Set Software Interrupt W 71E10000 System Pending Interrupt Register R 71E10004 System Interrupt Target Mask Register R 71E10008 System Interrup...

Page 52: ...tem Group Bit 31 MA Mask all Interrupts reserved in the System Interrupt Pending Register 1 disable all interrupts Bit 30 ME Module Error Bit 29 Reserved on SPARCbook Bit 28 Reserved on SPARCbook Bits...

Page 53: ...its to 0 Field definitions Bits 7 5 Reserved always read 0 Bit 4 I Modem Ring Interrupt Enable When this bit is set to 1 the modem RI interrupt generation is activated see also Bit 1 and the descripti...

Page 54: ...ARC mode 1 SuperSPARC 0 MicroSPARC II This bit determines the function of several multiplexed input pins the NCR89C105 unsufficient pins to support all functions concurrently The muxed pins are shown...

Page 55: ...0 The FPY_DENSENSE chip pin controls input bit Bit 5 The unused bits Bits 4 6 and 7 are unaffected by writes and always read 0 Bits 7 6 Reserved always read 0 Bit 5 D Floppy Density Sense not used Bi...

Page 56: ...this register or disabling PFD in the Config register clears this bit This bit is also set if BUFP or PWROK are set to 0 PFD input is ignored if Bit 5 is disabled in the Config register Bits 4 2 Rese...

Page 57: ...read as 0 Bits 7 3 Reserved always read 0 Bit 2 R RI pin This pin directly reflects the state of the MSI_IRQ_ pin which is used for modem RI when in Modem mode If this pin is low then this bit is 0 B...

Page 58: ...3 14 Memory Map and Interrupts NCR89C105 SLAVIO Configuration Control S3GX_TRMBook Page 14 Friday September 19 1997 11 39 am...

Page 59: ...One is a fully functional SCC and one has reduced functionality being intended for keyboard and mouse interfacing The architecture of the SPARCbook serial interface is shown in Figure 4 1 Figure 4 1 S...

Page 60: ...ce The SLAVIO internal registers appear on D 7 0 the data on the remainder of the bus during an SCC access is undefined A detailed programming discussion is beyond the scope of this manual for further...

Page 61: ...ions The Z82530 SCC contains fifteen write registers WR0 to WR15 for each channel WR8 is the transmit buffer and the remainder are used to configure the SCC for the required operation Two registers WR...

Page 62: ...r WR1 Transmit and Receive interrupt data transfer mode definitions WR2 Interrupt vector CH A and B WR3 Receive Parameters and controls WR4 Transmit and receive parameters and controls WR5 Transmit pa...

Page 63: ...terrupt enable Bit 0 External interrupt enable WR3 Receive Parameters and Control Bits 7 6 Bits character 00 5 bits 01 7 bits 10 6 bits 11 8 bits Bit 5 Auto enables Bit 4 Enter hunt mode Bit 3 Receive...

Page 64: ...eak Bit 3 Transmitter enable Bit 2 SDLC CRC 16 Bit 1 RTS Bit 0 Transmitter CRC enable WR9 Interrupt Control and Reset Bits 7 6 Reset control 00 no reset 01 Reset Channel B 10 Reset Channel A 11 Force...

Page 65: ...d Bits 4 3 Transmit clock source 00 01 Reserved 10 Baud rate generator 11 Reserved Bit 2 TRXC Enable Write 0 Bits 1 0 Not used WR14 Miscellaneous Control Bit 7 5 Clock Mode 000 Null 001 Enter search m...

Page 66: ...Bit 6 Transmit underrun EOM Bit 5 CTS Bit 4 Sync Hunt Bit 3 DCD Bit 2 Transmit Buffer empty Bit 1 Zero count interrupt enable Bit 0 Receive character available RR1 Special Receive Condition Bit 7 End...

Page 67: ...Bit 6 Two clocks missing Bit 4 Loop sending Bit 1 On loop Other bits 0 RR15 External Status Interrupt Status Bit 7 Break Abort interrupt enable Bit 6 Tx Underrun EOM interrupt enable Bit 5 CTS interr...

Page 68: ...19200 This is controlled by the clocking mode and the contents of the time constant register The value of the time constant can be determined using the following equation For example to set a baud rat...

Page 69: ...CSI 2 operations at up to 10 Mbytes sec running synchronously SCSI transfers are supported by the MACIO s integral DMA controller Figure 5 1 SCSI Architecture NCR 53C90 SBus SCSI SCSI Controller MACIO...

Page 70: ...ull support of ANSI X3 131 SCSI and SCSI 2 standard 5 2 1 53C9X register set The SCSI controller internal registers appear from base address 0x78800000 Table 5 1 shows the address offset of the SCSI i...

Page 71: ...Within the command code bits 6 4 control the operating mode of which only one can be selected at any time Bit 7 Enable DMA 0 DMA Mode Disabled 1 DMA Mode Enabled Bit 6 4 Select Mode see Table 5 2 An...

Page 72: ...t Sequence YES Target Mode Commands X 0 1 0 0 0 0 0 Send message YES X 0 1 0 0 0 0 1 Send status YES X 0 1 0 0 0 1 0 Send data YES X 0 1 0 0 0 1 1 Disconnect sequence YES X 0 1 0 0 1 0 0 Terminate seq...

Page 73: ...I transfer are in opposition or if there is an unexpected phase change in initiator role during a synchronous data phase Bit 5 Parity Error Bit 4 Terminal Count Bit 3 Valid Group Code Bits 2 0 SCSI Ph...

Page 74: ...ning in the FIFO Select Reconnect Register This is a 3 bit wide write only register used to specify the destination SCSI bus ID for a select or reselect command Clock Conversion Factor Register This r...

Page 75: ...FIFO until the largest possible Sbus burst write as specified in the DMA Controller s Control and Status register to memory can be carried out 5 3 2 DMA Registers The DMA controller provides four 32...

Page 76: ...5 8 SCSI Controller DMA Support S3GX_TRMBook Page 8 Friday September 19 1997 11 39 am...

Page 77: ...nto the MACIO This provides AUI connections via a 15 pin D shell connector The MACIO enhances Ethernet operations by providing DMA support Figure 6 1 Network Interface Architecture NCR 92C990 LAN Cont...

Page 78: ...overflow It allows internal and external loopback modes to be configured via the control registers Physical logical and promiscuous addressing modes are supported Packets can be received containing t...

Page 79: ...its D 15 2 are reserved The encoding of D 1 0 is shown in Table 6 2 6 2 2 Control and Status Register 0 This register contains control status error and interrupt information Address Register Size Acce...

Page 80: ...abled TD Transmit Demand STP Stop setting this bit causes the LAN controller to cease network activity This bit must also be set to allow access to the other Control and Status registers STP is reset...

Page 81: ...s a bit which determines the meaning of the valid dirty bit for that line These bits can be accessed in the Ethernet cache Valid Register Table 6 3 shows the DMA registers for network operations The s...

Page 82: ...6 6 Ethernet Interface DMA Support for Network Operations S3GX_TRMBook Page 6 Friday September 19 1997 11 39 am...

Page 83: ...erface between the CPU and microcontroller subsystem which provides battery management keybaord and mouse interfacing and initial power sequencing control The TS102 also provides interfaces for an ext...

Page 84: ...sfer sizes up to 8 word transfers but not 16 word and extended transfer modes The TS102 performs the required number of accesses to the PCMCIA interface to fulfill any request For example if the contr...

Page 85: ...lly contains the card configuration registers and I O space is used by I O cards such as network interface and modem cards The transfer cycle time is either fixed for release 1 0 compatible cards or i...

Page 86: ...ibute memory and I O space PCM_A 25 24 are driven from paging bits in the TS102 s register set The TS102 accepts byte halfword word doubleword quadword and octalword transfer requests and responds wit...

Page 87: ...implemented in the data routing block of the TS102 of which three are are of interest here They are dependent upon the transfer size and the two status bits per card indicating the byte ordering mode...

Page 88: ...ause the SLAVIO only permits read accesses to the EPROM in its conventional location However because the boot PROM is a FLASH device it is necessary to have write access to it so that can be reprogram...

Page 89: ...e to the boot PROM 7 3 TS102 Registers There are two separate register blocks within the TS102 The first gives access to PCMCIA card specific resources and the second gives access to the microcontroll...

Page 90: ...led when the mask is set to 1 and is cleared by writing a 1 to the associated clear bit The card interrupt registers also contain the soft reset flag Setting this bit to 1 will cause the SPARCbook 3 t...

Page 91: ...the card RDY BSY signal Note that this signal becomes IREQ on I O cards and the RDY BSY status may be available in the card pin replacement register if this bit is implemented in it Since the RDY BSY...

Page 92: ...ister if these bits are implemented in the card 00 battery low data suspect 01 battery low data suspect 10 battery low data OK 11 battery good Bit 8 WP Write Protect The WP bit indicates that the card...

Page 93: ...ks 9 7 OEW 2 0 OE WE width 111 000 2 clocks 001 3 clocks 010 4 clocks 011 5 clocks 100 6 clocks 101 7 clocks 110 8 clocks 111 9 clocks 10 CEH Chip enable hold time 1 0 1 clocks 1 2 clocks 11 SBLE SBus...

Page 94: ...rupt request 1 0 4 TXE_MSK Transmit FIFO empty mask 1 0 5 TXNF_MSK Transmit FIFO not full mask 1 0 6 RXNE_MSK Receive FIFO not empty mask 1 0 7 RXO_MSK Receive FIFO full mask 1 0 Table 7 8 Microcontr...

Page 95: ...ller s address space are shown in the table below Address Function 0x00 Host data register 0x01 Host interrupt register 0x02 Host status register 0x03 Not used 0x04 Command register 0x05 0x07 Not used...

Page 96: ...7 14 PCMCIA Interface Microcontroller Registers S3GX_TRMBook Page 14 Friday September 19 1997 11 39 am...

Page 97: ...These provide a terminal endpoint TE ISDN interface at the S T reference point and also high quality stereo audio The architecture of the ISDN and audio interface is illustrated in Figure 8 1 Figure...

Page 98: ...vices may share a single ISDN line to achieve virtually simultaneous operation Time division multiplexing is employed to superimpose both B channels and D channel together onto a differential wire pai...

Page 99: ...CHI Port The CHI port is used to connect the audio CODEC It provides a synchronous serial link which is used to transfer frames of audio data between the DBRI and audio CODEC The CHI uses four wires t...

Page 100: ...example audio data carried on one B channel from the TE interface could be routed through the CHI for audio output while data on the other B channel could be routed to the SBus interface for DMA into...

Page 101: ...maintained within the DBRI that define time slots for each interface A number of pipes are predefined as anchor pipes pipe 0 for the TE receive list pipe 1 for the TE transmit list and pipe 16 for th...

Page 102: ...es cannot be connected to the same data pipe in the same direction For the CHI the time slot descriptors must not define overlapping time slots CHI time slots that are greater than 32 bits long must c...

Page 103: ...E interface is synchronized with the network before the NT interface or CHI is active then the NT CHI is frequency locked with the TE when it is activated It is recommended for data transfer between T...

Page 104: ...et and cleared by the host If this bit is set the sanity timer is reset and disabled TO pin held high Clearing this bit restarts the sanity timer Bit 6 T Permit Activation of the TE Interface This bit...

Page 105: ...after the software reset This bit is also set by the hardware reset and cleared internally approximately 64 system clock cycles after the rising edge of the hardware reset Setting this bit initiates...

Page 106: ...Input Output 0 Not connected A bit port can be configured as an output by setting the associated enable bit Setting a PIO bit takes the associated bit port pin high REG3 Test Register This register i...

Page 107: ...10 8 illustrates the format of each command The more commonly used instructions are as follows IIQ Initialize interrupt queue SDP Setup data pipe Initialize a data pipe to carry time slots DTS Define...

Page 108: ...pt Queue REX Report command execution with interrupt 0 1 0 0 I Reserved Value SDP Setup data pipe 0 1 0 1 I Reserved IRM MODE D B P A C PIPE Pointer to Transmit or Receive Descriptor CDP Continue data...

Page 109: ...e descriptor buffers must be aligned on 4 word boundaries Figure 8 4 DBRI Data Structures OP CODE IIQ SDP SDP WAIT IQ POINTER OPTIONS AND PIPE TRANSMIT DESCRIPTOR TD POINTER TRANSMIT DESCRIPTOR TD POI...

Page 110: ...s as illustrated in Figure 8 6 which are used to generate a sampling clock for the internal analog to digital and digital to analog converters and can be programmed supply serial port timing The codec...

Page 111: ...igure 8 6 Audio Codec Clock Inputs XTAL2 CODEC XTAL1 24 576 MHz 16 9344 MHz Figure 8 7 Data and Control Mode Time Slots 1 2 3 4 5 6 7 8 16 bit 16 bit 8 bit 8 bit Control Status Data Serial Port Test P...

Page 112: ...the CLB bit in the Status register low 7 Read back and verify the control information from the codec mask reserved bits Wait for the CLB bit to go low 8 Set the CLB bit high and send at least to more...

Page 113: ...e slots to which the registers are assigned are shown in Table 8 4 The registers of most interest are described briefly below Status Register Bit 3 OLB Output Level Bit 0 Full scale outputs are Line 2...

Page 114: ...lection 00 16 bit law 01 8 bit law 10 8 bit A law 11 Reserved Serial Port Control Register Bit 7 ITS Immediate Tri State Bit DFR Crystal Source XTAL1 XTAL2 0 8 kHz 5 5125 kHz 1 16 kHz 11 025 kHz 2 27...

Page 115: ...Fs Bits 3 2 BSEL1 0 Select bit rate 00 64 bits per frame 01 128 bits per frame 10 256 bits per frame 11 reserved Bit 1 XCLK Transmit clock 0 Receive SCLK and FSYNC from external source 1 Generate SCL...

Page 116: ...t channel Audio data is transmitted MSB first and uses 2 s compliment coding In mono mode only the left channel data is used although both right and left DACs are driven In 8 bit modes only time slot...

Page 117: ...5 is MSB LO 0 represents 1 5 dB 0 no attenuation Intput Setting Bits 7 6 PIO bits Not used Bit 5 OVR Overrange This bit when set indiactes that an overrange condition has occured It remains set until...

Page 118: ...tion MA3 is the MSB MA0 represents 6 dB Full gain is at least 22 5 dB Not used in mono modes Bits 3 0 RG 3 0 Input gain for right channel RG3 is the MSB LGO represents 1 5 dB Full gain is 22 5 dB 0 no...

Page 119: ...o a telephone line is made via a data access arrangement DAA which provides the required line isolation Figure 9 1 shows the implementation of the modem interface in the SPARCbook 3 Figure 9 1 SPARCbo...

Page 120: ...isters The modem interface can be controlled using Hayes compatible commands written to the parallel interface of the MCU Commands are sent to the interface using character strings and these are inter...

Page 121: ...isconnect the telephone line During receive operations the host must read the data in the buffer in time for the next incoming character from the telephone line The Modem generates interrupts when the...

Page 122: ...terrupt Bit 1 Enable Transmitter Holding Register Empty Interrupt Bit 0 Enable Received Data Available Interrupt 9 3 2 Interrupt Identification Register This register provides the identity of the high...

Page 123: ...ool in the OpenWindows environment or with Unix commands from the Solaris command line It is also possible to interact with the modem directly using the Hayes compatible AT command set This section de...

Page 124: ...Code Wn Error Correction Message Control X Enable Extended Result Code Set Y Long Space Disconnect Fn Restore Factory Configuration V Display Current Configuration and Stored Profiles W Store Current...

Page 125: ...em have no effect on the operation of the SPARCbook modem A Answer Incoming Call This forces the modem to go off hook in answer mode A Re execute Previous Command This repeats the last command It is n...

Page 126: ...400 bps Hn Switch Hook Control n 0 Go on hook hang up n 1 Go off hook to access the telephone line In Identification This causes the modem to respond with identification codes n 0 Request Product Code...

Page 127: ...ration Store the currently active configuration including S registers as a profile n 0 or 1 Yn Designate a Default Profile Selects the profile used after a hardware reset Zn x Store Telephone Number T...

Page 128: ...y Callback Directory This causes the modem to supply a list of all callback directory entries P Store Callback Password This causes the modem to store a password and to store or delete a corresponding...

Page 129: ...ister can be changed using the Change S Register Command For example the command line ATS0 2 causes the modem to change the contents of S Register 0 to 2 S0 Number of Rings to Auto Answer Sets the num...

Page 130: ...mmand Options Status S24 Sleep Inactivity Timer S25 DTR Delay for Synchronous Operation S26 RTS CTS Delay S27 Command Options Status S28 Command Options Status S29 Flash Dial Modifier Time S30 Disconn...

Page 131: ...character and a second Backspace character this means a total of three characters are transmitted each time the modem accesses the Backspace character Range 0 127 ASCII decimal Default Backspace S6 Di...

Page 132: ...st Carrier To Hang Up Delay Sets the length of time in tenths of a second that the modem waits before hanging up after a loss of carrier This allows for a temporary carrier loss without causing the lo...

Page 133: ...0 Tone T default 1 Pulse P Bit 6 Reserved Bit 7 Originate Answer 0 Answer 1 Originate default S15 Reserved S16 General Bit Mapped Test Options Indicates the test in progress status Default 0 Bit 0 Loc...

Page 134: ...or H command Range 0 255 seconds Default 0 S19 S20 Reserved S21 V21 General Bit Mapped Options Indicates the status of command options Default 4 00000100b Bit 0 Set by Jn command but ignored otherwis...

Page 135: ...ke M3 Bit 4 5 6 Limit result codes Xn 0 X0 4 X1 5 X2 6 X3 7 X4 default Bit 7 Reserved S23 General Bit Mapped Options Indicates the status of command options Default 183 B7h 10110111b Bit 0 Grant RDL 0...

Page 136: ...nore DTR for before hanging up Its units are seconds for synchronous mode and one hundredths of a second for other modes Range 0 255 1 second for synchronous mode 1 0 01 second otherwise Default 5 S26...

Page 137: ...aling Pn 0 512 PO default 1 1024 P1 2 2048 P2 3 4096 P3 Bit 5 Reserved Bit 6 7 Reserved S29 Flash Dial Modifier Time Sets the length of time in units of 10 ms that the modem will go on hook when it en...

Page 138: ...II decimal Default 17 S33 XOFF Character Sets the value of the XOFF character Range 0 255 ASCII decimal Default 19 S34 35 Reserved S36 LAPM Failure Control Default 00000111b Bit 0 2 This value indicat...

Page 139: ...at 4800 bps F6 9 Attempt to connect at 9600 bps F8 10 Attempt to connect at 12000 bps F9 11 Attempt to connect at 14400 bps F10 12 Attempt to connect at 7200 bps F7 Bit 4 7 Reserved S38 Delay Before...

Page 140: ...apped Options Indicates the status of command options Default 105 69h 01101001b Bit 0 MNP Extended Services Kn 0 Disable extended services K0 1 Enable extended services K1 default Bit 1 Power Level Ad...

Page 141: ...ontrol Controls selection of compression The following actions are executed for the given values Range 136 or 138 Default 138 S46 136 Execute error correction protocol with no compression S46 138 Exec...

Page 142: ...lected Bit 1 Remote configuration permitted REMCONF signal 0 Remote configuration not permitted 1 Remote configuration permitted Bit 2 Call back security enforcement SECACC signal 0 Call back security...

Page 143: ...iled connection S86 records the first event that contributes to a NO CARRIER message The cause codes are Range 0 4 5 9 12 13 or 14 Default S86 0 Normal disconnect no error occurred S86 4 Loss of carri...

Page 144: ...gardless of the Wn setting Default 0 Bit 0 CONNECT result code indicates DCE speed instead of DTE speed Bit 1 Append ARQ to CONNECT XXXX result code if error correction is on Bit 2 Enable CARRIER XXXX...

Page 145: ...Report Current Session FDIS Report Remote Identification FCFR Indicate Confirmation to Receive FTSI Report the Transmit Station ID FCSI Report the Called Station ID FPTS Page Transfer Status FET Post...

Page 146: ...9 28 MODEM Class 2 Fax Command Set S3GX_TRMBook Page 28 Friday September 19 1997 11 39 am...

Page 147: ...0 0 0 The parallel interface on the SPARCbook is provided by the MACIO Figure 10 1 Parallel Port Architecture Parallel Port Interface DMA MACIO Buffers Sbus Parallel Port S3GX_TRMBook Page 1 Friday Se...

Page 148: ...dress register and byte counter are used The byte counter is enabled via the P_CSR and decrements each time a byte is transferred When the byte counter expires from 0x1 to 0 bit 9 in the P_CSR becomes...

Page 149: ...s set when the NEXT Address and Byte Count registers have been written but have not been used Bit 26 Address Loaded read only is set when the contents of the address and byte count are considered vali...

Page 150: ...s size of Pbus bursts Bits 17 15 Unused Bit 14 Terminal Count set when the byte count expires It is cleared by writing to logic 1 Bit 13 Enable Count when set enables the byte counter Bits 12 10 Unuse...

Page 151: ...e drives the built in LCD flat panel display and is able to drive an an external CRT display with resolutions of up to 1600 x 1200 pixels SPARCbook 3 is able to display simultaneously in the LCD and e...

Page 152: ...ernal displays The Power 9100 provides the host interface between the SBus and the frame buffer providing accelerated graphics operations for 8 16 and 32 bits per pixel The frame buffer comprises four...

Page 153: ...four 16 bit or two 32 bit pixels at a time Athough not implemented by the Solaris X Server the display hardware also supports 24 bit packed pixels The RAMDAC translates pixel data from the frame buffe...

Page 154: ...le properties via registers within the RAMDAC and Power 9100 which must be correctly programmed for the SPARCbook display interface to function correctly Display Synchronization The horizontal and ver...

Page 155: ...trolled by via internal registers and by command sent over the host interface bus It operates as a SBus slave The Power 9100 contains the following functional units Parameter engine Drawing engine Hos...

Page 156: ...s of host to screen BitBlt operations one is optimized for text and the other is optimized for graphics The parameter engine handles all exception testing and host accesses to parameter engine registe...

Page 157: ...e and VRAM sihift register size is controlled during power up by a number of pullup resistors connected to the frame buffer data ouptut pins This results in a 32 bin configuration word which is stored...

Page 158: ...registers are described briefly on the following pages However for a detailed description of the Power 9100 s registers and capabilities please refer to the Power 9100 data book see Appendix A Further...

Page 159: ...s 30 29 Shift Control 3 00 no add 01 add 1024 01 add 2048 11 add 4096 Bits 28 26 Pixel size 010 8 bits per pixel 011 16 bits per pixel 111 24 bits per pixel 101 32 bits per pixel Address Register Func...

Page 160: ...eld finaly set the shift control fields so that the total adds up to the number of bytes per scan line There are many possible combinations of which four examples are shown below Bits 13 11 Endian swa...

Page 161: ...0 not done 1 Vblank done Bits 3 Pick field write control Bit 4 Pick 0 not done 1 Pick done Bits 1 Idle field write control Bit 0 Drawing engine idle 0 Drawing engine busy 1 Drawing engine idle Interru...

Page 162: ...l This is used by the host to specify the total horizontal line length 3800010C Horizontal sync rising edge This register is used to specify where along the horizontal trace the rising edge of the hor...

Page 163: ...vertical blanking signal occurs 38000130 Vertical counter preload This read write register is used by the host to specify the value to load into the Vertical Counter when the vertical sync signal occ...

Page 164: ...0 Buffer 0 1 Buffer 1 Bits 2 0 QSF counter position Set to 011 Screen Repaint Timing Control Register The bits in this register are assigned as follows required settings are shown in bold type Bits 31...

Page 165: ...igured Must contain 0xC008007D 38000188 Refresh Period This read write register uses the lower 10 bits to specify the refresh period for the VRAM array 3800018C Refresh Count The lower 10 bits of this...

Page 166: ...16 bit Absolute value Y 1 38003068 32 bit Relative value for X 1 38003070 32 bit Relative value for Y 1 38003078 16 bit Relative value for X 1 and 16 bit Absolute value Y 1 38003088 32 bit Absolute v...

Page 167: ...t index into the x and y coordinates as a 2 bit binary integer The value is used for meta coordinate computation 38002190 Window Offset XY This read write register supplies the x and y offsets of the...

Page 168: ...1 y 3 y 3 y 0 y 2 y 3 y 1 y 2 y 0 y 1 Table 11 9 Vertex Checking Register Significant Bits Address Name Function 38002200 Foreground Color Contains an 8 bit value that specifies the foreground color 3...

Page 169: ...ved contain zeroes Bit 17 Pattern Enable 0 Disable pattern 1 Enable pattern Bit 16 Quick Draw Mode 0 X11 Mode 1 Oversized mode Bits 15 0 Minterms for boolean raster operations Window Minimum Maximum R...

Page 170: ...ft of the display pixel 0 is addressed at 0x30200000 The top left pixel on the display is fixed at this address in memory Panning and zooming is carried out by redrawing the image in the framebuffer P...

Page 171: ...hardware cursor digital outputs to drive an LCD display panel three digital to analog converters to drive a CRT display and a clock generator The the SPARCbook 3 implementation the device supports a...

Page 172: ...ister between each RAMDAC access The RAMDAC internal locations can be accessed using the addresses shown in Table 6 13 11 4 2 Control register accesses The control registers are used to program the RA...

Page 173: ...ccesses to the control registers This mechansim is usefull when writing to the cursor array for example but is not recommended when initailizing SPARCbook 3 because the registers are not programmed in...

Page 174: ...63 for 50 MHz 0017 001F Reserved 0020 F1 M0 0021 F1 N0 0022 F2 M1 0023 F3 N1 0024 F4 M2 0025 F5 N2 0026 F6 M3 0027 F7 N3 0028 F8 M4 0029 F9 N4 002A F10 M5 002B F11 N5 002C F12 M6 002D F13 N6 002E F14...

Page 175: ...5f Reserved 0060 Border Color Red 0061 Border Color Green 0062 Border Color Blue 0063 006F Reserved 1 0070 Miscellanous Control 1 0x11 2 0071 Miscellanous Control 2 0x45 3 0072 Miscellanous Control 3...

Page 176: ...n using 8 or 16 BPP but must contain 0x80 when using 24 or 32 BPP This causes the RAMDAC to swap the red and blue pixels to correct for endian differences between the frame buffer and RAMDAC Miscellan...

Page 177: ...ins 0x00 to select linear palette mode bit 7 System Clock Control Index 0x0008 This register is used to control the SYSCLK phase locked loop and signal pin Bit 6 is programmed to zero to enable the SY...

Page 178: ...olor lookup table is made The second address count increments the address register after each access to the blue entry This is illustrated in Figure 6 8 For example to write a new set of color informa...

Page 179: ...in a monochrome image on the external display 16 BPP When 16 bit pixels are in use four pixels are obtainde for each pixel port data cycle Color information can be organized as 5 bits for each color...

Page 180: ...11 30 Display Interface RAMDAC S3GX_TRMBook Page 30 Friday September 19 1997 11 39 am...

Page 181: ...the following Monitoring and controlling initial system power up Handling keyboard and pointing stick input Monitoring battery condition and charging Monitoring the unit s thermal envorinment Handling...

Page 182: ...ed with dedicated system management software Figure 12 1 Microcontroller Subsystem Architecture TS102 Case Switch Keyboard Scanning Real Time Clock Serial EEPROM DUART External Keyboard External Mouse...

Page 183: ...its main code loop This loop incorporates the the following operations 1 Checking for host commands from TS102 2 Checking for keyboard and mouse commands 3 Scanning the internal keyboard 4 Scanning t...

Page 184: ...y a high gain amplifier before being applied to analog to digital converters in the microcontroller The dc bias of the amplifiers is software adjustable via a digital potentiometer allowing pointing s...

Page 185: ...oller generate s to indicate for example that a low power shutdown is imminent Using a command set the host is able to select the display contents and cause them to be displayed Messages may be altere...

Page 186: ...are returned in order major minor 0x04 Read Microcontroller Version none ack 2 bytes The Microcontroller Version is hardwired into the microcontroller firmware It is described by two byte values retur...

Page 187: ...its environment The interpretation placed on this bitmask is shared with system software The defined values are as follows Bit 0 Shutdown request Bit 1 Battery event low power warning Bit 2 Battery ev...

Page 188: ...interrupt character 0xFA The host uses the Read Event Status command 0x0C to read the error status and clear the error bit 0x00 No error 0x01 Command error 0x02 Execution error 0x04 Physical error 0x...

Page 189: ...ack 1 byte This command reads the voltage on the bridge for the horizontal pointer 0x17 Read Vertical Pointer Voltage PTRVERV ack 1 byte This command reads the voltage on the bridge for the vertical p...

Page 190: ...board type first byte and layout information second byte for an external keyboard attached to the unit If no external keyboard is attached both fields are set to KB_UNKNOWN 0xFF 0x1E ReadEEPROM Status...

Page 191: ...Function 0x20 Control LCD mask ack 2 bytes The host controls the LCD via this command Setting a bit activates the approriate symbol on the unit s LCD panel Bit 0 Caps lock Bit 1 Scroll lock Bit 2 Num...

Page 192: ...d by Read Reset Status will be watchdog reset The watchdog period is expressed in seconds from 1 255 dec A setting of zero 0 indicates that the watchdog is to be suspended This is the default state af...

Page 193: ...feature is activated The following bit values are currently defined 0x1 Display command interface diagnostics on LCD 0x2 Set keyboard and mouse ports to 9600 baud 0x2F Control Screen Contrast mask ack...

Page 194: ...alue returned by Read Reset Status after the unit is reset will be software reset 0x35 Set Real Time Clock 7 bytes sec min hr day date mon yr ack This command is used by system software to initialize...

Page 195: ...rotected then the status byte will indicate the error condition 0x42 Write to Status Display length offset data ack This command writes a string to the status display The offset argument is used to de...

Page 196: ...ontrast UP 0x95 LCD Contrast DOWN 0x96 Speaker Volume UP 0x97 Speaker Volume DOWN 0x98 Display Next Status It should be noted that scan codes in this range and above are invalid Complete key sequences...

Page 197: ...rform EMU Command command ack The host controls the Energy Management Unit by sending commands to it through this interface The microcontroller does not interpret these commands 0x65 Read EMU Register...

Page 198: ...ey The microcontroller will return the value from the RTC It will also retain the values which are returned for use in the Verify System Password command 0x73 Verify System Password length password ac...

Page 199: ...mation A A A This appendix provides a list of publications or websites to which you can refer for further information about components used in the SPARCbook 3 S3GX_TRMBook Page 1 Friday September 19 1...

Page 200: ...I O External keyboard mouse interface interrupt controller EBus controller MK48T08 Real time clock SRAM Memory Products Databook 3rd Edition June 1994 SGS Thomson Electronics http www st com Weitek P...

Page 201: ...Connector Information B B B This appendix provides a pinouts for the connectors used the SPARCbook 3 S3GX_TRMBook Page 1 Friday September 19 1997 11 39 am...

Page 202: ...r SPARCbook 3 are shielded types Refer to page iii of this User Guide if interference is suspected B 1 1 DCIn B 1 2 Parallel S3XP S3GX and S3TX The following connector is fitted on the I O panel of th...

Page 203: ...TA 3 22 DATA 6 8 DATA 5 23 Signal Ground 9 Signal Ground 24 ACK 10 DATA 7 25 Signal Ground 11 Signal Ground 26 PE 12 BUSY 27 Signal Ground 13 SELECT 28 AUTOFEED 14 Signal Ground 29 INIT 15 ERROR 30 Si...

Page 204: ...round 9 COLLISION 2 COLLISION 10 TRANSMIT DATA 3 TRANSMIT DATA 11 Chassis Ground 4 Chassis Ground 12 RECEIVE DATA 5 RECEIVE DATA 13 12Va 6 Chassis Ground 14 Chassis Ground 7 Not Connected 15 Not Conne...

Page 205: ...nal Ground 32 SCSI D 6 8 Signal Ground 33 SCSI D 7 9 Signal Ground 34 SCSI D PARITY 10 Signal Ground 35 Signal Ground 11 Signal Ground 36 Signal Ground 12 Not Used 37 Not Used 13 Not Used 38 SCSI TERM...

Page 206: ...SCSI REQ 7 SCSI D 3 22 Signal Ground 8 Signal Ground 23 SCSI BSY 9 SCSI ACK 24 Signal Ground 10 Signal Ground 25 SCSI ATN 11 SCSI D 4 26 SCSI CD 12 Signal Ground 27 SCSI RST 13 Signal Ground 28 SCSI...

Page 207: ...nnector Pin Signal Pin Signal 1 Not Connected 5 TE IN 2 Not Connected 6 TE OUT 3 TE OUT 7 Not Connected 4 TE IN 8 Not Connected 1 6 2 3 4 5 7 8 Connector Pin Signal Pin Signal 1 Not Connected 4 TIP 2...

Page 208: ...k 3 models Connector Pin Signal Pin Signal 1 STROBE 14 AUTOFEED 2 DATA 0 15 ERROR 3 DATA l 16 INIT 4 DATA 2 17 SELECT_IN 5 DATA 3 18 Signal Ground 6 DATA 4 19 Signal Ground 7 DATA 5 20 Signal Ground 8...

Page 209: ...CD 4 24 SCSID 7 SCSISEL 5 25 GND SCSIREQ 6 26 SCSID 6 SCSIRST 7 27 GND SCSIMSG 8 28 SCSID 5 SCSIIACK 9 29 GND SCSIATN 10 30 SCSID 4 GND 11 31 GND SCSIBSY 12 32 SCSID 3 GND 13 33 GND SCSITPWR 14 34 SCS...

Page 210: ...B 10 Connector Information Removable Hard Drive SCSI Connector S3GX_TRMBook Page 10 Friday September 19 1997 11 39 am...

Page 211: ...oller and MMU 2 8 card interrupt registers PCMCIA 7 8 card status registers PCMCIA 7 9 class 2 fax command set 9 27 clock SCC 4 10 color palette accesses 11 28 command register SCSI 5 3 command set mi...

Page 212: ...erface 1 10 Ebus description 1 7 Ethernet DMA registers 6 5 DMA support 6 5 Ethernet controller 1 11 control and status register 0 6 3 control and status register 1 and 2 6 4 control and status regist...

Page 213: ...pes 8 4 ISDN interface 8 1 L LCD power 11 4 LCD status display 12 5 LED Floppy Aux 1 Register 3 11 linked lists ISDN 8 6 logic states definition xi M MACIO 1 10 address space 3 2 diagnostic message re...

Page 214: ...ap 11 8 SVGA unit 11 7 system control registers 11 9 video control registers 11 12 VRAM control registers 11 15 Power 9100 commands 11 8 Power 9100 User Interface Controller 11 5 power down register M...

Page 215: ...unications controllers 4 1 SLAVIO expansion interface TS102 7 6 SLAVIO general description 3 3 slow I O subsystem overview 1 9 SPARCbook 3 address map 3 2 status and control registers Power 9100 11 8...

Page 216: ...Index vi S3GX_TRMBook Page vi Friday September 19 1997 11 39 am...

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