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DBRI Overview
Long pipes can be configured to pass data through transparently or to code
or decode data as HDLC frames. The CCITT Q921 protocol requires that
protocol information is coded as HDLC formatted packets whereas payload
data on the B channels does not require processing.
In HDLC mode, long pipes perform CRC generation and checking and
automatically handle abort conditions.
Short pipes are only used to connect serial interfaces (e.g. CHI and TE).
They cannot be used for DMA. The 32 bits of buffering provided by short
pipes is adequate for transfer between serial interfaces because they are
synchronized to a master clock with little unpredictable latency between the
ports.
To maintain synchronization, some pipes are assigned as anchor pipes.
With two serial interfaces active, there needs to be four anchor pipes. These
pipes are the beginning points of linked lists maintained within the DBRI
that define time slots for each interface. A number of pipes are predefined
as anchor pipes: pipe 0 for the TE receive list; pipe 1 for the TE transmit
list; and pipe 16 for the CHI receive and transmit lists (for DMA to the CHI,
link a long pipe to the anchor pipe).
Data can enter a pipe in three ways:
•
From a data structure in memory via DMA.
•
From a time slot on one of the serial interfaces, as defined by a
time-slot descriptor (TSD) associated with the data pipe.
•
Fixed data can be set by the Set Short Pipe Data (SSP) command.
Similarly, data can leave a pipe in three ways:
•
To a data structure in memory via DMA.
•
To a time slot on one of the serial interfaces as defined by a TSD
associated with the data pipe.
•
A change in fixed data can be reported on the interrupt queue.
Any data pipe which is DMA or fixed on one end must be serial on the other
end.
In the monitor mode, serial input from one time slot can go to two pipes. In
the noncontiguous mode, multiple time slots from a serial interface can be
assigned to the same pipe
S3GX_TRMBook Page 5 Friday, September 19, 1997 11:39 am
Summary of Contents for SPARCbook 3 series
Page 8: ...viii S3GX_TRMBook Page viii Friday September 19 1997 11 39 am...
Page 44: ...2 16 The SPARC CPU SBus Controller S3GX_TRMBook Page 16 Friday September 19 1997 11 39 am...
Page 76: ...5 8 SCSI Controller DMA Support S3GX_TRMBook Page 8 Friday September 19 1997 11 39 am...
Page 146: ...9 28 MODEM Class 2 Fax Command Set S3GX_TRMBook Page 28 Friday September 19 1997 11 39 am...
Page 180: ...11 30 Display Interface RAMDAC S3GX_TRMBook Page 30 Friday September 19 1997 11 39 am...
Page 216: ...Index vi S3GX_TRMBook Page vi Friday September 19 1997 11 39 am...