Tadpole SPARCbook 3 series, Reference Manual

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The SPARC CPU
2-11
Cache Controller and Memory Management Unit
Page Table Pointer The PTP contains the physical address of a page table in memory, and can
be found in the context table, or in a level 1 or 2 page table. Page tables are
loaded into the TLB during tablewalks, and are removed by tablewalks or
flushing.
Bits 31:27 Reserved – always write 0
Bits 26:4 PTP – Physical address of the next page table.
Bits 3:2 Reserved – always 00.
Bits 1:0 ET – Entry type, contains 01 to denote a PTP.
I/O Page Table Entry The I/O PTE defines the physical address of a page and its access
permission.
Bits 31:27 Reserved – always write 0
Bits 26:8 PPN – Physical Page Number, which provides the upper 19
bits (30:12) of the 31-bit physical address of the page.
Bits 7:3 Reserved – always contains 0000
Bit 2 Writeable
0 = read only
1 = read/write
Bit 1 This bit is set to 1 when the I/OPTE is valid
Bit 0 This bit is to be written as zero (WAZ) in the Memory I/O
Page Table by software.
2.4.2 Address translation
During an access by the IU, the virtual address supplied by the IU and the
contents of the context register are compared with the virtual section of all
TLB entries. When a match is found (or a “hit” occurs), the Physical section
supplies the address of a page in memory, or a pointer to a page table in
physical memory. Virtual address bits A(11:00) from the IU are passed
through unchanged to supply a byte offset. Each hit TLB entry is
automatically checked for memory protection attributes and violations are
reported to the IU as memory exceptions.
If the virtual address from the IU does not match an entry in the TLB, the
MMU automatically performs a search (or table walk) through a translation
table in main memory to obtain an address translation. The translation table
forms a tree structure in the main memory. An example of this is illustrated
in Figure 2-5.
S3GX_TRMBook Page 11 Friday, September 19, 1997 11:39 am