Tadpole SPARCbook 3 series, Reference Manual

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6-4
Ethernet Interface
LAN Controller Registers
ERR Error – a logical “OR” of BAB, CE, MISS and ME
BAB Babble – Transmitter timeout error
CE Collision Error
MISS Missed Packet
ME Memory Error – LAN controller unable to access memory
as bus master.
RINT Receiver Interrupt – set when a packet is received, or if a
receive error has occurred.
TINT Transmit Error – set when a transmission is completed or
due to a transmit error.
IFIN Initialization Finished
INT Interrupt Pending
IEN Interrupt Enable – when set, interrupt requests are enabled.
RON Receiver On – receiver has been enabled
TON Transmitter On – transmitter has been enabled
TD Transmit Demand
STP Stop – setting this bit causes the LAN controller to cease
network activity. This bit must also be set to allow access to
the other Control and Status registers. STP is reset by INIT
or STR
STR Start – setting this bit enables the transmitter and receiver
and buffer management parts of the LAN controller. It also
clears the STP bit.
INIT Initialize – setting this bit causes the LAN controller to
begin an initialization process.
6.2.3 Control and Status Register 1 and 2
These two registers combine to provide the 24 bit address of the
initialization block. CRS1 contains the low order 16 bits, and CSR2
contains the upper 8 bits. The initialization block should always be aligned
on a word boundary; i.e. bit 0 of CSR1 should contain 0.
S3GX_TRMBook Page 4 Friday, September 19, 1997 11:39 am