Tadpole SPARCbook 3 series, Reference Manual

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10-4
Parallel Interface
Parallel Port Control Registers
Bit 25 DMA On (read-only) – when set, indicates that DMA
transfers are not disabled due to any hardware or software
condition.
Bit 24 Enable Next (R/W) – when set enables DMA chaining, and
autoloading of NEXT registers.
Bit 23 Terminal Count Interrupt Disable (R/W) – when set disables
terminal count from generating an interrupt.
Bits 22:21 Unused
Bit 20 When set, disables draining and resetting of FIFO when the
address register is loaded.
Bits 19:18 Pbus Burst Size – defines size of Pbus bursts
Bits 17:15 Unused
Bit 14 Terminal Count – set when the byte count expires. It is
cleared by writing to logic ‘1’.
Bit 13 Enable Count – when set enables the byte counter.
Bits 12:10 Unused
Bit 9 Enable DMA – when set, enables DMA
Bit 8 DMA Direction
0 = to memory
1 = from memory
Bit 7 Parallel Port Reset
Bit 6 Slave Error – when set indicates that an access-size error
occurred to a parallel port register
Bit 5 Invalidate FIFO (write-only).
Bit 4 Interrupt Enable – when set, enables interrupts generated by
the parallel port.
Bits 3:2 Draining – both bits are set when the FIFO is draining,
otherwise both bits are ‘0’.
Bit 1 Error Pending
Bit 0 Interrupt Pending
S3GX_TRMBook Page 4 Friday, September 19, 1997 11:39 am