Tadpole SPARCbook 3 series, Reference Manual, Page: 32 / 216

2-4
The SPARC CPU
Integer Unit
The arithmetic, logical and shift instructions compute a result that is a
function of one or two source operands and then place the result
non-destructively in a register.
The control transfer instruction category includes jumps, calls, traps, and
branches. Control transfers are usually delayed until after execution of the
next instructions so that the pipeline is not emptied every time a control
transfer occurs, allowing compilers to optimize for delayed branching.
The read/write control register instructions include instructions to read and
write the contents of various control registers. Generally, the source or
destination is implied by the instruction.
2.2.3 Traps and interrupts
The SPARC design supports a full set of traps and interrupts. They are
handled by a table that supports 128 hardware and 128 software traps. Even
though floating-point instructions can execute concurrently with integer
instructions, floating-point traps are precise because the FPU supplies
(from the table) the address of the instruction that failed.
INSTRUCTION CYCLES
Call 1
Single Loads 1
Jump/Return 2
Double Loads 2
Single Stores 1
Double Stores 2
Taken Trap 3
Atomic Load/Store 2
SWAP 2
Integer Multiply 19
Integer Divide 39
All Others 1
Table 2-1 IU Cycles per Instruction
S3GX_TRMBook Page 4 Friday, September 19, 1997 11:39 am