The SPARC CPU
2-15
SBus Controller
2.8.1
Programmed I/O
Programmed I/O transactions consist of an SBus slave cycle only, with
address translations being carried out before bus acquisition. The processor
executes loads and stores to transfer data between it and devices on the
SBus (in I/O Space). The SBus Controller performs write posting during
processor writes, allowing processing to continue while the SBus
transaction is completed. During reads, processing is stalled until the data
becomes valid at the end of the SBus transaction.
2.8.2
DVMA
A direct virtual memory access consists of a translation cycle followed by
a slave cycle. During the translation cycle, a master places a virtual address
on the SBus data bus. The SPARC’s MMU provides a translated physical
address on the SBus.
S3GX_TRMBook Page 15 Friday, September 19, 1997 11:39 am
Summary of Contents for SPARCbook 3 series
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Page 44: ...2 16 The SPARC CPU SBus Controller S3GX_TRMBook Page 16 Friday September 19 1997 11 39 am...
Page 76: ...5 8 SCSI Controller DMA Support S3GX_TRMBook Page 8 Friday September 19 1997 11 39 am...
Page 146: ...9 28 MODEM Class 2 Fax Command Set S3GX_TRMBook Page 28 Friday September 19 1997 11 39 am...
Page 180: ...11 30 Display Interface RAMDAC S3GX_TRMBook Page 30 Friday September 19 1997 11 39 am...
Page 216: ...Index vi S3GX_TRMBook Page vi Friday September 19 1997 11 39 am...