Tadpole SPARCbook 3 series, Reference Manual

Page: 81 / 216

Ethernet Interface
6-5
DMA Support for Network Operations
6.2.4 Control and Status Register 3
This register is used to set the LAN controller operating parameters to suit
its hardware environment. It is programmed by the resident firmware
during system start-up and should not be changed.
6.3 DMA Support for Network Operations
The MACIO’s DMA core provides additional registers for controlling
network related DMA operations. Between the network interface and Sbus
interface, there is a 2 line 8 word/line cache with consistency control logic.
Each byte in the cache has an associated valid/dirty bit, and each line has a
bit which determines the meaning of the valid/dirty bit for that line. These
bits can be accessed in the Ethernet cache Valid Register.
Table 6-3 shows the DMA registers for network operations.
The selection between 10Base5, 10Base2 and 10BaseT is determined by a
bit port within the MACIO. However, OpenBoot automatically selects
between the interfaces.
Figure 6-3 Control and Status Registers 1 and 2
15
1
Initialization Block Address (15:1) 0
0
15
0
Reserved
Initialization Block Address (23:16)
Address Register Size Access
0x784000010 Ethernet Control and Status Register 32 R/W
0x784000014 Ethernet Test Control Registers 32 R/W
0x784000018 Cache Valid Bits 32 R/W
0x78400001C Ethernet Base Address Register 8 R/W
Table 6-3 DMA Registers for Network Operations
S3GX_TRMBook Page 5 Friday, September 19, 1997 11:39 am