Tadpole SPARCbook 3 series, Reference Manual

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PCMCIA Interface
7-5
TS102 Memory Mapping
asserts its WAIT signal, the TS102 slave interface responds with a retry
acknowledgment to the master, and then continues with the PCMCIA
transfer cycle.
Similarly, burst accesses to slow PCMCIA cards can cause a single burst
access to take longer than 10
µ
s, and in these cases the TS102 responds with
a retry acknowledgment. The TS102 checks subsequent cycles by
comparing the address, size and direction to ensure that the new cycle is the
retried cycle, and not a new and different cycle. Any other new cycle
attempted to the PCMCIA slave interface must be rerun as it cannot be
attempted until after the retried PCMCIA cycle is complete.
7.2.2 Byte Swapping
The TS102 supports programmable byte-swapping, to allow the use of big
or little-endian PCMCIA cards. The two PCMCIA card interfaces in the
TS102 have individually programmable byte swapping, although it is not
advisable to program the two differently.
Four byte-swapping modes are implemented in the data routing block of the
TS102, of which three are are of interest here. They are dependent upon the
transfer size, and the two status bits per card indicating the byte ordering
mode. One status bit provides endian control for the normally big-endian
SBus interface, and the other status bit provides endian control for the
PCMCIA card. The details of these modes are shown in theTable 7-2. Data
on the left is the SBus data, and data on the right is the PCMCIA data.
Accesses to the I/O and attribute spaces are handled differently. The
attribute space is byte wide and only even addressed bytes exist, while
accesses to I/O space must be treated as bytes unless the I/O card responds
Size
SBus BE
PCMCIA LE
SBus LE
PCMCIA LE
Sbus BE
PCMCIA BE
SBus LE
PCMCIA LE
Byte D[31:24] <-> D[7:0] D[31:24} <-> D[7:0] D[31:24] <-> D[7:0] D[31:24] <-> D[7:0]
Halfword D[31:16] <-> D[15:0] D[31:24] <-> D[7:0]
D[23:16] <-> D[15:8]
D[31:24] <-> D[7:0]
D[23:16] <-> D[15:8] D[31:16] <-> D[15:0]
Word D[31:0] <-> D[31:0] D[31:24] <-> D[7:0]
D[23:16] <-> D[15:8]
D[15:8] <-> D[23:16]
D[7:0] <-> D[31:24]
D[31:24] <-> D[7:0]
D[23:16] <-> D[15:8]
D[15:8] <-> D[23:16]
D[7:0] <-> D[31:24] D[31:0] <-> D[31:0]
Table 7-2 Sbus to PCMCIA Data Routing
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