Tadpole SPARCbook 3 series, Reference Manual

Page: 154 / 216

11-4
Display Interface
Display Interface Overview
Pixel clocks The RAMDAC incorporates a programmable pixel clock generator, which
allows the pixel clock to be programmed to suit a large range of display
formats. In the SPARCbook 3 application, the RAMDAC generates a
master pixel clock controlled by values in the Pixel PLL Rate Registers.
The master pixel clock is fed into the P9100 which generates the horizontal
and vertical synchronization signals.
The Power 9100 also provides serial clock signals which are used to clock
pixel information out of the serial access port of the frame buffer. Thse are
generated from divided pixel clock supplied by the RAMDAC. The
frequency of divided pixel clock is a function of the number of pixels within
each 64-bit transfer from the frame buffer. For example, if the pixel bus is
organized as eight 8-bit pixels, the require serial clock rate must be supplied
at
1
/
8
of the dot clock frequency.
The serial clock and multiplexer rates are configurable properties via
registers within the RAMDAC and Power 9100 which must be correctly
programmed for the SPARCbook display interface to function correctly.
Display
Synchronization The horizontal and vertical sync signals from the Power 9100 are connected
to some gating logic where they are combined to provide a composite synch
signal. The composite sync and vertical sync are both fed into the
RAMDAC to control display timing.
The SPARCbook 3 is able to supply an external display with separate
horizontal and vertical sync signals or supply a composite sync
superimposed on the green video channel (sync-on-green). Sync-on-green
operation is controlled by the RAMDAC and can be enabled using the
microcontroller’s Control Bitport command, see Section 12.2.3,
“Read/Write/Modify Commands”, on page 12-11.
11.1.3 LCD Power
Power to the built-in LCD display is controlled by the microcontroller
using the microcontroller’s Control Bitport command, see Section 12.2.3,
“Read/Write/Modify Commands”, on page 12-11. In order for the display
to function correctly, the digital outputs from the RAMDAC should be
enbabled before enabling the TFT display.
S3GX_TRMBook Page 4 Friday, September 19, 1997 11:39 am