Tadpole SPARCbook 3 series, Reference Manual

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Memory Map and Interrupts
3-9
NCR89C105 SLAVIO Configuration Control
Bit 17 Reserved
Bit 16 E – Ethernet Interrupt
Bit 15 Bit S – Serial Port Interrupt (SLAVIO)
Bit 14 K – Keyboard/Mouse Interrupt
Bits 13:07 SBus IRQ (7:1)
Bits 06:00 Reserved
3.3 NCR89C105 SLAVIO Configuration Control
3.3.1 SLAVIO Configuration Register
The NCR89C105 has several software-programmable options which are
controlled by its configuration register. This register is located at
0x70180000.
A system reset clears all of the SLAVIO configuration bits to 0.
Field definitions:
Bits 7:5 Reserved - always read 0.
Bit 4 I - Modem Ring Interrupt Enable. When this bit is set to 1,
the modem RI interrupt generation is activated (see also Bit
1, and the description of the modem register). When this bit
is cleared, modem interrupts are not generated, regardless of
the state of the M bit (Bit 1) or the MSI_IRQ_input.
Bit 3 P - Power Fail Detect Enable. When this bit is set to 1, a low
on the PFD_input causes a module error (error 15) interrupt.
The interrupt is visible (and clearable) in AuxIO register 2.
When this bit is clear, the PFD_input is ignored.
Figure 3-3 The SLAVIO Configuration Register
Reserved P D M S
7 6 5 4 3 2 1 0
I
S3GX_TRMBook Page 9 Friday, September 19, 1997 11:39 am