Tadpole SPARCbook 3 series, Reference Manual

Page: 121 / 216

MODEM
9-3
Interface Control
The MCU registers are accessible at base address 0x0F0280000 and are
shown in Table 11-1.
Bit 7 in the Line Control register is used as a pointer to either the Transmit
and Receive Buffers and the Interrupt Enable register, or to the Divisor
Latch registers. Bit 7 must be at ‘0’ for access to the Transmit and Receive
Buffers, or at ‘1’ for access to the Interrupt Enable register and Divisor
Latch.
The host is responsible for managing the transmit and receive buffers.
During transmit operations, the host must supply data at a sufficient rate to
ensure that there is always a new character for the modem to transmit; the
modem is unable to wait and will regard an empty buffer as an error
condition and disconnect the telephone line. During receive operations, the
host must read the data in the buffer in time for the next incoming character
from the telephone line.
The Modem generates interrupts when the receive buffer contains a
character, when the transmit buffer is empty, and also to signal error
conditions. All interrupt requests within the SPARCbook are maskable and
are prioritized by the SLAVIO, see Section 3.2, “Interrupts”, on page 3-5.
ADDRESS REGISTER ACCESS
0F0280000 Receive Buffer Read-only
Transmit Buffer Write-only
Divisor Latch (LSB) Read-Write
0F0280001 Interrupt Enable Read-Write
Divisor Latch (MSB) Read-Write
0F0280002 Interrupt Identity Read-only
0F0280003 Line Control Read-Write
0F0280004 Modem Control Read-Write
0F0280005 Line Status Read-Write
0F0280006 Modem Status Read-Write
0F0280007 Scratch Pad Register Read-Write
Table 9-1 Modem Control Registers
S3GX_TRMBook Page 3 Friday, September 19, 1997 11:39 am