Tadpole SPARCbook 3 series, Reference Manual

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Serial Interface
4-3
SCC Registers
4.2 SCC Registers
The SCC internal registers are accessed using a register pointer to perform
selection. First, the register pointer bits in WR0 are programmed to specify
the register to be accessed. Then, a read or a write is performed at the same
address to transfer data into or out of the selected register. When the access
to the selected register has been completed, the register pointer bits are reset
to ‘0’.
Three pointer bits in WR0 allow access to the lower eight registers
locations, but WR0 also contains 3-bit command word (D5:D3) in which
the ‘Point High’ command, 001(bin), is required to gain access to the upper
eight register locations. The receive buffer and transmit buffer, RR8 and
WR8 respectively for each channel can be accessed in a single read or write
operation.
4.2.1 Register functions
The Z82530 SCC contains fifteen write registers (WR0 to WR15) for each
channel. WR8 is the transmit buffer and the remainder are used to configure
the SCC for the required operation. Two registers (WR2 and WR9) are
shared by both channels. Each channel also has nine read registers (RR0 to
RR3, RR8, RR10, RR12, RR13 and RR15). RR8 is the receive buffer and
the remainder provide status information.
Table 4-11 shows the full suite of registers present in the external 85C30
SCC and full-function internal SCC. The sub-set SCC does not present the
full set of registers.
Register Function
RR0 Transmit and Receive Buffer status, external status
RR1 Special receive condition status
RR2A, RR2B Unmodified interrupt vector (Ch A only), Modified interrupt vector (Ch B only)
RR3A, RR3B Interrupt pending bits (Ch A only), Null (Ch B only)
RR8 Receive Buffer
RR10 Miscellaneous status
RR12 Lower byte of baud-rate time constant
RR13 Upper byte of baud-rate time constant
Table 4-2 SCC Register Summary
S3GX_TRMBook Page 3 Friday, September 19, 1997 11:39 am