Tadpole SPARCbook 3 series, Reference Manual

Page: 46 / 216

3-2
Memory Map and Interrupts
Address Map
3.1 Address Map
The SBus controller contained in the MicroSPARC partitions the
SPARCbook 3’s memory map into a region for the main memory plus five
physical address regions of 256Mbytes each for the SBus. The resulting
memory map of the SPARCbook is shown in Table 3-1.
3.1.1 MACIO and SLAVIO Space (SBus Slot 4)
SBus slot 4 is sub-divided to provide access to the MACIO and SLAVIO.
These two devices are designed to operate as a pair, and each device has a
direct SBus connection.
The MACIO device incorporates DMA controllers, an Ethernet controller,
a bi-directional parallel interface, and a SCSI bus controller. The DMA
controllers provide support for the Ethernet, parallel and SCSI interfaces,
including FIFO support, and allow burst transfers to be performed on the
SBus.
Connected to the SLAVIO but isolated from the SBus are the Boot ROM,
the O/S ROMs, the RTC and NVRAM, modem and Audio devices.
Address Range
(Hexadecimal)
Region SBus Rsource
Size
(Mbytes)
70000000 7FFFFFFF SBus Slot 4 MACIO/SLAVIO 256
60000000 6FFFFFFF SBus Slot 3 Not allocated 256
50000000 5FFFFFFF SBus Slot 2 ISDN Controller 256
40000000 4FFFFFFF SBus Slot 1 TS102 PCMCIA Controller 256
30000000 3FFFFFFF SBus Slot 0 P9100 Graphics Controller 256
20000000 2FFFFFFF Unmapped - 256
10000000 1FFFFFFF I/O MMU Control Space - 256
08000000 0FFFFFFF Unmapped - 128
06000000 07FFFFFF DRAM Bank 3 - 32
04000000 05FFFFFF DRAM bank 2 - 32
02000000 03FFFFFF DRAM Bank 1 - 32
00000000 01FFFFFF DRAM Bank 0 - 32
Table 3-1 Main Memory Map
S3GX_TRMBook Page 2 Friday, September 19, 1997 11:39 am