Tadpole SPARCbook 3 series, Reference Manual

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Memory Map and Interrupts
3-7
Interrupts
3.2.1 Interrupt Control
The SLAVIO provides a number of interrupts status and control locations.
The processor group provides interrupt pending information and control
over software interrupts. The system group provides enable and clearing
control over the individual hardware interrupt requests.
Processor Group
Address
(Hexadecimal
)
Device or Register Access
71E00000 Processor Interrupt Pending R
71E00004 Processor Clear Pending W
71E00008 Processor Set Software Interrupt W
71E10000 System Pending Interrupt Register R
71E10004 System Interrupt Target Mask Register R
71E10008 System Interrupt Target Mask Clear W
71E1000C System Interrupt Target Mask Set W
Table 3-7 Interrupt Control Registers
Figure 3-1 Processor Interrupt Registers
Processor Interrupt Pending Register
Processor Interrupt Clear Pseudo-register
Processor Set Soft Interrupt Pseudo Register
31 17 16 15 00 01
SOFTINT(15:1) HARDINT(15:1)
SOFTINT(15:1) CLEAR
SOFTINT(15:1) SET
IC
31
31
17
17
16
16
00
00
15
S3GX_TRMBook Page 7 Friday, September 19, 1997 11:39 am