Tadpole SPARCbook 3 series, Reference Manual

Page: 163 / 216

Display Interface
11-13
Power 9100 User Interface Controller
Screen Repaint Timing
Control Register 1
The bits in this register are assigned as follows (required settings are shown
in bold type):
Bits 31:11 Reserved
Bits 10:9 SRADDR increment size
00 = 256
01 = 512
10 = 1024
Bit 8 VSYNC source
0 = External
1 = Internal
38000120 Vertical Length This is used by the host to specify the number of lines in a
vertical trace.
38000124 Vertical sync rising edge This register is used to specify where along the vertical trace
the rising edge of the horizontal sync signal occurs.
38000128 Vertical blank rising edge This register is used to specify where along the vertical trace
the rising edge of the vertical blanking signal occurs.
3800012C Vertical blank falling edge This register is used to specify where along the vertical trace
the falling edge of the vertical blanking signal occurs.
38000130 Vertical counter preload This read-write register is used by the host to specify the
value to load into the Vertical Counter when the vertical sync
signal occurs.
Screen repaint
38000134 Screen repaint address This read-only register specifies the next VRAM address to
be loaded into SAM. The address corresponds to bits (21:10)
of the linear address (the lower address bits are always zero).
The value occupies the lower 12 bits.
38000138 Screen repaint timing control1 Specifies controls for screen refresh – must contain 0x1A3 –
see below.
3800013C QSF Counter This read-only register counts the QSF signals from the
VRAMs to keep track of which part of the SAM is being
shifted out. It is loaded with zero after every read transfer and
is incremented by each dot clock
38000140 Screen repaint timing control2 Specifies controls for screen refresh – must contain 0x5 –
see below.
Address Register Function
Table 11-5 Video Control Registers Summary (Continued)
S3GX_TRMBook Page 13 Friday, September 19, 1997 11:39 am