Tadpole SPARCbook 3 series, Reference Manual

Page: 112 / 216

8-16
ISDN and 16-bit Audio
Audio CODEC
The steps required to move the audio codec from data to control mode and
then back again are as follows:
1. Lower the output level to maximum attenuation.
2. Mute the speaker output
3. Take the D/C pin low.
4. If the codec is timing master and the ITSD bit in the serial port control
register is ‘0’, wait at least 12 SCLK periods to allow SCLK and
FSYNC to tri-state
5. Drive the serial clock and frame sync signals into the audio codec.
6. Send control data as required with the CLB bit in the Status register
low.
7. Read back and verify the control information from the codec. mask
reserved bits. Wait for the CLB bit to go low.
8. Set the CLB bit high and send at least to more frames. This causes the
codec to ignore any further activity on the bus. Also, the serial data out
pin will be held in a highimpedence state afrter transmitteing one
frame with the CLB bit high.
9. If the codec is progarmmed to be timing master, set the DBRI to
receive SLK and FSYNC from the codec.
10. Set up new audio data to be transmitted to the codec
Figure 8-8 Frame Timing
1 2 8 9 10 16 17 18 64 65
Slot 1 Slot 2 Slot 3 Slot 8
DATA
FSYNC
SCLK
(TSIN)
S3GX_TRMBook Page 16 Friday, September 19, 1997 11:39 am