Tadpole SPARCbook 3 series, Reference Manual

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Display Interface
11-3
Display Interface Overview
The page-mode VRAM device is a type of memory chip specifically
designed for use in display memories which provides a read-write random
access port through which the CPU and P9100 can perform graphics
operations, and a serial port through which image data is output for display
by RAMDAC. Picture information is moved a page at a time from the
random access area of the VRAM to the serial access memory (SAM) area
within the VRAM chips and then shifted out at high speed to the RAMDAC
under the control of a timing signals from the Power 9100.
The RAMDAC and frame buffer are connected via a 64-bit pixel data bus.
Pixel data can be read in by the RAMDAC as eight 8-bit, four 16-bit or two
32-bit pixels at a time. Athough not implemented by the Solaris X Server,
the display hardware also supports 24-bit packed pixels. The RAMDAC
translates pixel data from the frame buffer into digital color information
which is used to drive the LCD display directlty, or routed through three
D-to-A converters to produce the analog signals required to drive an
external video display.
The control register interface, which is used to configure the RAMDAC for
the required operation, is accessed via locations within the Power9100
address space.
11.1.2 Display Interface Timing
Figure 11-2 Display Interface Timing
Pixel Clock
VSync
Screen Blanking
Controls
Address
Data
Pixel
2MB
Power
RGB528
RAMDAC
Serial Clocks
VRAM
P9100
HSync
CSync
CSync Enable (from
µ
controller)
Gating
Logic
VSync
HSync
Sync-on-Green
Digital Clock
External
CRT
Internal
LCD
Data
S3GX_TRMBook Page 3 Friday, September 19, 1997 11:39 am