Tadpole SPARCbook 3 series, Reference Manual

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3-12
Memory Map and Interrupts
NCR89C105 SLAVIO Configuration Control
Power Down Control (Aux 2) Register
All Bits are cleared to 0 on system reset.
Bits 7:6 Reserved. These bits should be masked, and their values
should be discarded by the software. These bits can be read
and written to, but the values have no meaning or effect.
Bit 5 D - Power Failure Detect (1 = power fail). When the power
fail detect signal from the power supply is low, this bit is set,
and a module error interrupt is generated (this is a level 15
interrupt). Writing a 1 to Bit 1 of this register, or disabling
PFD in the Config register clears this bit. This bit is also set
if BUFP or PWROK are set to 0.
PFD* input is ignored if Bit 5 is disabled in the Config
register.
Bits 4:2 Reserved. These bits should be masked, and their values
should be discarded by the software. These bits can be read
and written to, but the values have no meaning or effect.
Bit 1 C - Clear Power Fail Detect (1 = clear). This bit clears the
interrupt generated by PFD_ and Bit 5 of this register.
Writing 0 has no effect.
Bit 0 F - Power off (1 = off). This bit is reflected in the power
output pin. When this bit is set to 1, the power supply turns
off.
Figure 3-6 Auxiliary I/O Register 2
D
7 6 5 4 3 2 1 0
C F
S3GX_TRMBook Page 12 Friday, September 19, 1997 11:39 am