Tadpole SPARCbook 3 series, Reference Manual

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6-2
Ethernet Interface
NCR92C990 Overview
6.1 NCR92C990 Overview
The NCR92C990 is a LAN controller which supports the parameters for an
IEEE 802.3 network interface.
6.1.1 Bus Interface
The LAN controller operates as a bus master or a bus slave device.
As a slave, it provides a 16-bit control interface on the SBus with two
register locations. The CPU accesses the registers during system
initialization, and in response to interrupts. Additional registers in the
MACIO’s DMA controller provide enhanced support for programming
DMA operations.
As a master, it operates independently using DMA operations to transfer
data between the network and data structures in memory. The LAN
controller incorporates two independent 48-byte FIFOs; one for transmit
operations, and one for receive operations.
6.1.2 LAN Interface
The NCR92C990 supports error reporting for diagnostics, addressing,
collision, jabbering, framing, underflow and overflow. It allows internal
and external loopback modes to be configured via the control registers.
Physical, logical and promiscuous addressing modes are supported.
Packets can be received containing the full 48-bit destination address for
matching against a physical address programmed during initialization. The
LAN controller will also allow the programming of 64 logical addresses for
matching with an incoming packet’s address header. In the promiscuous
mode, all incoming error free packets are accepted and stored in memory.
6.1.3 Descriptor Management
Buffer management for the LAN controller is handled by a recurrent list of
assignments in memory called descriptor rings. There are separate
descriptor rings for transmit and receive operations. The decriptor rings are
searched to determine the location of the next empty buffer. After a buffer
is filled, the OWN bit in the corresponding descriptor is set. When the
controller detects that the OWN bit is set in a descriptor, it uses the ring
buffer pointer in that descriptor to locate the next data buffer.
S3GX_TRMBook Page 2 Friday, September 19, 1997 11:39 am