Tadpole SPARCbook 3 series, Reference Manual, Page: 30 / 216

2-2
The SPARC CPU
SPARC Architecture Overview
2.1 SPARC Architecture Overview
The SPARC processor is a highly integrated device which provides the
following features:
• SPARC compliant V8 Integer Unit core
• SPARC Reference Memory Management Unit
• MEIKO Floating Point Unit
• 16 Kbyte Instruction Cache
• 8 or 16 Kbyte Data Cache
• Memory Controller
• SBus Controller, Master and Slave Interface
Figure 2-1 MicroSPARC-II Architecture
Integer
Floating Point
Instruction
Cache
Data
Cache
Write Buffer
4 Entry
MMU
64 entry
64 bit Cache Fill Bus
Memory
Interface
SBC
32 bit SBus
Main Memory
inst[31:0]
dpc[31:2]
fp_dout_e[63:0]
iu_dout[63:0]
Instr
d_va[31:0]
i_va{31:0]
Phy_addr[27:0]
Misc_Bus[31:0]
memdata<63:0>
Unit Unit
S3GX_TRMBook Page 2 Friday, September 19, 1997 11:39 am