Tadpole SPARCbook 3 series, Reference Manual

Page: 37 / 216

The SPARC CPU
2-9
Cache Controller and Memory Management Unit
2.4.1 Translation lookaside buffer
The Memory Management Unit (MMU) conforms to the standard SPARC
architecture definition for memory management.
The MMU provides virtual to physical address translation using a
translation lookaside buffer (TLB). An entry in the TLB has the fields
shown in Figure 2-4.
TLB Entry Fields
Virtual Address Tag
represents the most significant 20 bits, VA(31:12), of the
virtual address.
Context Tag
is compared with the 6-bit context number in the context
register written by memory management software.
Prot Six protection bits in each TLB entry represent the decoded
ACC bits from the matching PTE. These are: User Rd, Wr,
Ex, and Supervisor Rd, Wr, Ex.
Level This 3-bit field is used to allow the proper tag match of
region and segment PTEs. I/O PTEs and PTPs 1 will have
this field set to use index 1, 2, and 3. The most significant bit
also serves as the TLB Valid Bit because it is set for any
valid PTE, I/OPTE or PTP.
000 = none
100 = Index 1 –VA(31:24)
110 = Index 1,2 – VA(31:18)
111 = index 1,2,3 – VA(31:12)
S Supervisor – This bit disables matching of the context field
of a page in supervisor level.
M This is set to 1 if page is written.
I/O PTE This bit, when ‘0’, indicates that an I/O PTE is contained in
this entry.
Figure 2-4 TLB Entry
Virtual Address Tag Context Tag Level S IO PTP Page Table Field M UW SR SW UR SE UE
Prot
S3GX_TRMBook Page 9 Friday, September 19, 1997 11:39 am